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tcg/mips: implement deposit op on MIPS32R2

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deposit operations can be optimized on MIPS32 Release 2 using the INS
instruction.

Reviewed-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
This commit is contained in:
Aurelien Jarno 2012-09-21 18:20:26 +02:00
parent 9a152519a9
commit 04f71aa3fd
2 changed files with 10 additions and 1 deletions
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8
tcg/mips/tcg-target.c
View File

@ -328,6 +328,7 @@ enum {
OPC_BGEZ = OPC_REGIMM | (0x01 << 16), OPC_BGEZ = OPC_REGIMM | (0x01 << 16),
OPC_SPECIAL3 = 0x1f << 26, OPC_SPECIAL3 = 0x1f << 26,
OPC_INS = OPC_SPECIAL3 | 0x004,
OPC_WSBH = OPC_SPECIAL3 | 0x0a0, OPC_WSBH = OPC_SPECIAL3 | 0x0a0,
OPC_SEB = OPC_SPECIAL3 | 0x420, OPC_SEB = OPC_SPECIAL3 | 0x420,
OPC_SEH = OPC_SPECIAL3 | 0x620, OPC_SEH = OPC_SPECIAL3 | 0x620,
@ -1455,6 +1456,11 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc,
tcg_out_ext16s(s, args[0], args[1]); tcg_out_ext16s(s, args[0], args[1]);
break; break;
case INDEX_op_deposit_i32:
tcg_out_opc_imm(s, OPC_INS, args[0], args[2],
((args[3] + args[4] - 1) << 11) | (args[3] << 6));
break;
case INDEX_op_brcond_i32: case INDEX_op_brcond_i32:
tcg_out_brcond(s, args[2], args[0], args[1], args[3]); tcg_out_brcond(s, args[2], args[0], args[1], args[3]);
break; break;
@ -1550,6 +1556,8 @@ static const TCGTargetOpDef mips_op_defs[] = {
{ INDEX_op_ext8s_i32, { "r", "rZ" } }, { INDEX_op_ext8s_i32, { "r", "rZ" } },
{ INDEX_op_ext16s_i32, { "r", "rZ" } }, { INDEX_op_ext16s_i32, { "r", "rZ" } },
{ INDEX_op_deposit_i32, { "r", "0", "rZ" } },
{ INDEX_op_brcond_i32, { "rZ", "rZ" } }, { INDEX_op_brcond_i32, { "rZ", "rZ" } },
{ INDEX_op_setcond_i32, { "r", "rZ", "rZ" } }, { INDEX_op_setcond_i32, { "r", "rZ", "rZ" } },
{ INDEX_op_setcond2_i32, { "r", "rZ", "rZ", "rZ", "rZ" } }, { INDEX_op_setcond2_i32, { "r", "rZ", "rZ", "rZ", "rZ" } },

3
tcg/mips/tcg-target.h
View File

@ -86,7 +86,6 @@ typedef enum {
#define TCG_TARGET_HAS_orc_i32 0 #define TCG_TARGET_HAS_orc_i32 0
#define TCG_TARGET_HAS_eqv_i32 0 #define TCG_TARGET_HAS_eqv_i32 0
#define TCG_TARGET_HAS_nand_i32 0 #define TCG_TARGET_HAS_nand_i32 0
#define TCG_TARGET_HAS_deposit_i32 0
#define TCG_TARGET_HAS_movcond_i32 0 #define TCG_TARGET_HAS_movcond_i32 0
/* optional instructions only implemented on MIPS32R2 */ /* optional instructions only implemented on MIPS32R2 */
@ -94,10 +93,12 @@ typedef enum {
#define TCG_TARGET_HAS_bswap16_i32 1 #define TCG_TARGET_HAS_bswap16_i32 1
#define TCG_TARGET_HAS_bswap32_i32 1 #define TCG_TARGET_HAS_bswap32_i32 1
#define TCG_TARGET_HAS_rot_i32 1 #define TCG_TARGET_HAS_rot_i32 1
#define TCG_TARGET_HAS_deposit_i32 1
#else #else
#define TCG_TARGET_HAS_bswap16_i32 0 #define TCG_TARGET_HAS_bswap16_i32 0
#define TCG_TARGET_HAS_bswap32_i32 0 #define TCG_TARGET_HAS_bswap32_i32 0
#define TCG_TARGET_HAS_rot_i32 0 #define TCG_TARGET_HAS_rot_i32 0
#define TCG_TARGET_HAS_deposit_i32 0
#endif #endif
/* optional instructions automatically implemented */ /* optional instructions automatically implemented */