First RISC-V PR for QEMU 8.0
* Fix PMP propagation for tlb * Collection of bug fixes * Bump the OpenTitan supported version * Add smstateen support * Support native debug icount trigger * Remove the redundant ipi-id property in the virt machine * Support cache-related PMU events in virtual mode * Add some missing PolarFire SoC io regions * Fix mret exception cause when no pmp rule is configured * Fix bug where disabling compressed instructions would crash QEMU * Add Zawrs ISA extension support * A range of code refactoring and cleanups -----BEGIN PGP SIGNATURE----- iQEzBAABCAAdFiEE9sSsRtSTSGjTuM6PIeENKd+XcFQFAmO3b5sACgkQIeENKd+X cFTD8Af+L0OaGzE4C0jil7LdITFKk7ltdTg3yw84ZBvIxrEWMWlt5Yj3Ez5OIPbY WpPmCLoJ9XM/5CV5PuPjxcFFExWjXLNeMEvaaT/3/3jPPnA/M/AbZa4hefKRluTg kkvBiOuRMPXiYLki5xAHmjD/1j6SQ8ghylPLxYQqyGq87WZt4Dx9msOTZLVzmmYl 8y9oC8j6yO2UBZYC1TxSkKxFbj+Cp2HmtBZ09tDzwRL6DpRvIlfftiLl8X3awMlK YTzCIrmllc38/+cV9IpQhdXzDUZ1kM7Zy56JbJl3XOsS4VnUYGmEtrKYpYQ2CKLY /tcmrDKNw1ArWcP1axNN8FHfhy1FyQ== =SH+C -----END PGP SIGNATURE----- Merge tag 'pull-riscv-to-apply-20230106' of https://github.com/alistair23/qemu into staging First RISC-V PR for QEMU 8.0 * Fix PMP propagation for tlb * Collection of bug fixes * Bump the OpenTitan supported version * Add smstateen support * Support native debug icount trigger * Remove the redundant ipi-id property in the virt machine * Support cache-related PMU events in virtual mode * Add some missing PolarFire SoC io regions * Fix mret exception cause when no pmp rule is configured * Fix bug where disabling compressed instructions would crash QEMU * Add Zawrs ISA extension support * A range of code refactoring and cleanups # gpg: Signature made Fri 06 Jan 2023 00:47:23 GMT # gpg: using RSA key F6C4AC46D4934868D3B8CE8F21E10D29DF977054 # gpg: Good signature from "Alistair Francis <alistair@alistair23.me>" [full] # Primary key fingerprint: F6C4 AC46 D493 4868 D3B8 CE8F 21E1 0D29 DF97 7054 * tag 'pull-riscv-to-apply-20230106' of https://github.com/alistair23/qemu: (43 commits) hw/intc: sifive_plic: Fix the pending register range check hw/riscv: opentitan: Drop "hartid-base" and "priority-base" initialization hw/intc: sifive_plic: Change "priority-base" to start from interrupt source 0 hw/riscv: virt: Fix the value of "riscv, ndev" in the dtb hw/riscv: sifive_u: Avoid using magic number for "riscv, ndev" hw/riscv: sifive_e: Fix the number of interrupt sources of PLIC hw/riscv: microchip_pfsoc: Fix the number of interrupt sources of PLIC hw/intc: sifive_plic: Update "num-sources" property default value hw/intc: sifive_plic: Use error_setg() to propagate the error up via errp in sifive_plic_realize() hw/intc: sifive_plic: Improve robustness of the PLIC config parser hw/intc: sifive_plic: Drop PLICMode_H hw/riscv: spike: Remove misleading comments hw/riscv: Sort machines Kconfig options in alphabetical order hw/riscv: Fix opentitan dependency to SIFIVE_PLIC hw/intc: Select MSI_NONBROKEN in RISC-V AIA interrupt controllers hw/riscv: Select MSI_NONBROKEN in SIFIVE_PLIC RISC-V: Add Zawrs ISA extension support target/riscv: Clear mstatus.MPRV when leaving M-mode for priv spec 1.12+ target/riscv: Simplify helper_sret() a little bit target/riscv: Set pc_succ_insn for !rvc illegal insn ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Peter Maydell
commit
052e6534c4
@ -72,12 +72,15 @@ config RISCV_ACLINT
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config RISCV_APLIC
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bool
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select MSI_NONBROKEN
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config RISCV_IMSIC
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bool
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select MSI_NONBROKEN
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config SIFIVE_PLIC
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bool
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select MSI_NONBROKEN
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config GOLDFISH_PIC
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bool
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@ -42,7 +42,6 @@ static PLICMode char_to_mode(char c)
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switch (c) {
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case 'U': return PLICMode_U;
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case 'S': return PLICMode_S;
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case 'H': return PLICMode_H;
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case 'M': return PLICMode_M;
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default:
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error_report("plic: invalid mode '%c'", c);
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@ -78,6 +77,7 @@ static uint32_t sifive_plic_claimed(SiFivePLICState *plic, uint32_t addrid)
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uint32_t max_irq = 0;
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uint32_t max_prio = plic->target_priority[addrid];
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int i, j;
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int num_irq_in_word = 32;
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for (i = 0; i < plic->bitfield_words; i++) {
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uint32_t pending_enabled_not_claimed =
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@ -88,7 +88,16 @@ static uint32_t sifive_plic_claimed(SiFivePLICState *plic, uint32_t addrid)
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continue;
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}
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for (j = 0; j < 32; j++) {
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if (i == (plic->bitfield_words - 1)) {
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/*
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* If plic->num_sources is not multiple of 32, num-of-irq in last
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* word is not 32. Compute the num-of-irq of last word to avoid
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* out-of-bound access of source_priority array.
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*/
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num_irq_in_word = plic->num_sources - ((plic->bitfield_words - 1) << 5);
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}
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for (j = 0; j < num_irq_in_word; j++) {
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int irq = (i << 5) + j;
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uint32_t prio = plic->source_priority[irq];
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int enabled = pending_enabled_not_claimed & (1 << j);
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@ -131,10 +140,11 @@ static uint64_t sifive_plic_read(void *opaque, hwaddr addr, unsigned size)
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SiFivePLICState *plic = opaque;
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if (addr_between(addr, plic->priority_base, plic->num_sources << 2)) {
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uint32_t irq = ((addr - plic->priority_base) >> 2) + 1;
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uint32_t irq = (addr - plic->priority_base) >> 2;
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return plic->source_priority[irq];
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} else if (addr_between(addr, plic->pending_base, plic->num_sources >> 3)) {
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} else if (addr_between(addr, plic->pending_base,
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(plic->num_sources + 31) >> 3)) {
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uint32_t word = (addr - plic->pending_base) >> 2;
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return plic->pending[word];
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@ -178,7 +188,7 @@ static void sifive_plic_write(void *opaque, hwaddr addr, uint64_t value,
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SiFivePLICState *plic = opaque;
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if (addr_between(addr, plic->priority_base, plic->num_sources << 2)) {
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uint32_t irq = ((addr - plic->priority_base) >> 2) + 1;
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uint32_t irq = (addr - plic->priority_base) >> 2;
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if (((plic->num_priorities + 1) & plic->num_priorities) == 0) {
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/*
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@ -193,7 +203,7 @@ static void sifive_plic_write(void *opaque, hwaddr addr, uint64_t value,
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sifive_plic_update(plic);
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}
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} else if (addr_between(addr, plic->pending_base,
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plic->num_sources >> 3)) {
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(plic->num_sources + 31) >> 3)) {
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qemu_log_mask(LOG_GUEST_ERROR,
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"%s: invalid pending write: 0x%" HWADDR_PRIx "",
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__func__, addr);
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@ -281,7 +291,7 @@ static void sifive_plic_reset(DeviceState *dev)
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*/
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static void parse_hart_config(SiFivePLICState *plic)
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{
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int addrid, hartid, modes;
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int addrid, hartid, modes, m;
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const char *p;
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char c;
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@ -290,11 +300,13 @@ static void parse_hart_config(SiFivePLICState *plic)
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p = plic->hart_config;
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while ((c = *p++)) {
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if (c == ',') {
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if (modes) {
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addrid += ctpop8(modes);
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modes = 0;
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hartid++;
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modes = 0;
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}
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} else {
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int m = 1 << char_to_mode(c);
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m = 1 << char_to_mode(c);
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if (modes == (modes | m)) {
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error_report("plic: duplicate mode '%c' in config: %s",
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c, plic->hart_config);
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@ -305,8 +317,9 @@ static void parse_hart_config(SiFivePLICState *plic)
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}
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if (modes) {
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addrid += ctpop8(modes);
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}
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hartid++;
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modes = 0;
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}
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plic->num_addrs = addrid;
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plic->num_harts = hartid;
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@ -317,11 +330,16 @@ static void parse_hart_config(SiFivePLICState *plic)
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p = plic->hart_config;
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while ((c = *p++)) {
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if (c == ',') {
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if (modes) {
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hartid++;
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modes = 0;
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}
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} else {
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m = char_to_mode(c);
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plic->addr_config[addrid].addrid = addrid;
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plic->addr_config[addrid].hartid = hartid;
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plic->addr_config[addrid].mode = char_to_mode(c);
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plic->addr_config[addrid].mode = m;
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modes |= (1 << m);
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addrid++;
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}
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}
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@ -346,6 +364,11 @@ static void sifive_plic_realize(DeviceState *dev, Error **errp)
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parse_hart_config(s);
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if (!s->num_sources) {
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error_setg(errp, "plic: invalid number of interrupt sources");
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return;
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}
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s->bitfield_words = (s->num_sources + 31) >> 5;
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s->num_enables = s->bitfield_words * s->num_addrs;
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s->source_priority = g_new0(uint32_t, s->num_sources);
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@ -362,7 +385,8 @@ static void sifive_plic_realize(DeviceState *dev, Error **errp)
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s->m_external_irqs = g_malloc(sizeof(qemu_irq) * s->num_harts);
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qdev_init_gpio_out(dev, s->m_external_irqs, s->num_harts);
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/* We can't allow the supervisor to control SEIP as this would allow the
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/*
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* We can't allow the supervisor to control SEIP as this would allow the
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* supervisor to clear a pending external interrupt which will result in
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* lost a interrupt in the case a PLIC is attached. The SEIP bit must be
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* hardware controlled when a PLIC is attached.
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@ -370,8 +394,8 @@ static void sifive_plic_realize(DeviceState *dev, Error **errp)
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for (i = 0; i < s->num_harts; i++) {
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RISCVCPU *cpu = RISCV_CPU(qemu_get_cpu(s->hartid_base + i));
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if (riscv_cpu_claim_interrupts(cpu, MIP_SEIP) < 0) {
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error_report("SEIP already claimed");
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exit(1);
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error_setg(errp, "SEIP already claimed");
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return;
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}
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}
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@ -402,8 +426,10 @@ static const VMStateDescription vmstate_sifive_plic = {
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static Property sifive_plic_properties[] = {
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DEFINE_PROP_STRING("hart-config", SiFivePLICState, hart_config),
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DEFINE_PROP_UINT32("hartid-base", SiFivePLICState, hartid_base, 0),
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DEFINE_PROP_UINT32("num-sources", SiFivePLICState, num_sources, 0),
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/* number of interrupt sources including interrupt source 0 */
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DEFINE_PROP_UINT32("num-sources", SiFivePLICState, num_sources, 1),
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DEFINE_PROP_UINT32("num-priorities", SiFivePLICState, num_priorities, 0),
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/* interrupt priority register base starting from source 0 */
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DEFINE_PROP_UINT32("priority-base", SiFivePLICState, priority_base, 0),
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DEFINE_PROP_UINT32("pending-base", SiFivePLICState, pending_base, 0),
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DEFINE_PROP_UINT32("enable-base", SiFivePLICState, enable_base, 0),
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@ -476,11 +502,11 @@ DeviceState *sifive_plic_create(hwaddr addr, char *hart_config,
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CPUState *cpu = qemu_get_cpu(cpu_num);
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if (plic->addr_config[i].mode == PLICMode_M) {
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qdev_connect_gpio_out(dev, num_harts - plic->hartid_base + cpu_num,
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qdev_connect_gpio_out(dev, cpu_num - hartid_base + num_harts,
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qdev_get_gpio_in(DEVICE(cpu), IRQ_M_EXT));
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}
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if (plic->addr_config[i].mode == PLICMode_S) {
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qdev_connect_gpio_out(dev, cpu_num,
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qdev_connect_gpio_out(dev, cpu_num - hartid_base,
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qdev_get_gpio_in(DEVICE(cpu), IRQ_S_EXT));
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}
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}
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@ -24,6 +24,7 @@
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#include "qemu/bitops.h"
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#include "qemu/log.h"
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#include "qapi/error.h"
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#include "hw/irq.h"
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#include "hw/sysbus.h"
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#include "hw/misc/mchp_pfsoc_ioscb.h"
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@ -33,6 +34,10 @@
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*/
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#define IOSCB_WHOLE_REG_SIZE 0x10000000
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#define IOSCB_SUBMOD_REG_SIZE 0x1000
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#define IOSCB_CCC_REG_SIZE 0x2000000
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#define IOSCB_CTRL_REG_SIZE 0x800
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#define IOSCB_QSPIXIP_REG_SIZE 0x200
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/*
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* There are many sub-modules in the IOSCB module.
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@ -44,7 +49,10 @@
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#define IOSCB_LANE01_BASE 0x06500000
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#define IOSCB_LANE23_BASE 0x06510000
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#define IOSCB_CTRL_BASE 0x07020000
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#define IOSCB_QSPIXIP_BASE 0x07020100
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#define IOSCB_MAILBOX_BASE 0x07020800
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#define IOSCB_CFG_BASE 0x07080000
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#define IOSCB_CCC_BASE 0x08000000
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#define IOSCB_PLL_MSS_BASE 0x0E001000
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#define IOSCB_CFM_MSS_BASE 0x0E002000
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#define IOSCB_PLL_DDR_BASE 0x0E010000
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@ -141,6 +149,58 @@ static const MemoryRegionOps mchp_pfsoc_io_calib_ddr_ops = {
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.endianness = DEVICE_LITTLE_ENDIAN,
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};
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#define SERVICES_CR 0x50
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#define SERVICES_SR 0x54
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#define SERVICES_STATUS_SHIFT 16
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static uint64_t mchp_pfsoc_ctrl_read(void *opaque, hwaddr offset,
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unsigned size)
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{
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uint32_t val = 0;
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switch (offset) {
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case SERVICES_SR:
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/*
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* Although some services have no error codes, most do. All services
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* that do implement errors, begin their error codes at 1. Treat all
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* service requests as failures & return 1.
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* See the "PolarFire® FPGA and PolarFire SoC FPGA System Services"
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* user guide for more information on service error codes.
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*/
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val = 1u << SERVICES_STATUS_SHIFT;
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break;
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default:
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qemu_log_mask(LOG_UNIMP, "%s: unimplemented device read "
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"(size %d, offset 0x%" HWADDR_PRIx ")\n",
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__func__, size, offset);
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}
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return val;
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}
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static void mchp_pfsoc_ctrl_write(void *opaque, hwaddr offset,
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uint64_t value, unsigned size)
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{
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MchpPfSoCIoscbState *s = opaque;
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switch (offset) {
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case SERVICES_CR:
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qemu_irq_raise(s->irq);
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break;
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default:
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qemu_log_mask(LOG_UNIMP, "%s: unimplemented device write "
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"(size %d, value 0x%" PRIx64
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", offset 0x%" HWADDR_PRIx ")\n",
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__func__, size, value, offset);
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}
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}
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static const MemoryRegionOps mchp_pfsoc_ctrl_ops = {
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.read = mchp_pfsoc_ctrl_read,
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.write = mchp_pfsoc_ctrl_write,
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.endianness = DEVICE_LITTLE_ENDIAN,
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};
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static void mchp_pfsoc_ioscb_realize(DeviceState *dev, Error **errp)
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{
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MchpPfSoCIoscbState *s = MCHP_PFSOC_IOSCB(dev);
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@ -160,14 +220,26 @@ static void mchp_pfsoc_ioscb_realize(DeviceState *dev, Error **errp)
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"mchp.pfsoc.ioscb.lane23", IOSCB_SUBMOD_REG_SIZE);
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memory_region_add_subregion(&s->container, IOSCB_LANE23_BASE, &s->lane23);
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memory_region_init_io(&s->ctrl, OBJECT(s), &mchp_pfsoc_dummy_ops, s,
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"mchp.pfsoc.ioscb.ctrl", IOSCB_SUBMOD_REG_SIZE);
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memory_region_init_io(&s->ctrl, OBJECT(s), &mchp_pfsoc_ctrl_ops, s,
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"mchp.pfsoc.ioscb.ctrl", IOSCB_CTRL_REG_SIZE);
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memory_region_add_subregion(&s->container, IOSCB_CTRL_BASE, &s->ctrl);
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memory_region_init_io(&s->qspixip, OBJECT(s), &mchp_pfsoc_dummy_ops, s,
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"mchp.pfsoc.ioscb.qspixip", IOSCB_QSPIXIP_REG_SIZE);
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memory_region_add_subregion(&s->container, IOSCB_QSPIXIP_BASE, &s->qspixip);
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memory_region_init_io(&s->mailbox, OBJECT(s), &mchp_pfsoc_dummy_ops, s,
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"mchp.pfsoc.ioscb.mailbox", IOSCB_SUBMOD_REG_SIZE);
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memory_region_add_subregion(&s->container, IOSCB_MAILBOX_BASE, &s->mailbox);
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memory_region_init_io(&s->cfg, OBJECT(s), &mchp_pfsoc_dummy_ops, s,
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"mchp.pfsoc.ioscb.cfg", IOSCB_SUBMOD_REG_SIZE);
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memory_region_add_subregion(&s->container, IOSCB_CFG_BASE, &s->cfg);
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memory_region_init_io(&s->ccc, OBJECT(s), &mchp_pfsoc_dummy_ops, s,
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"mchp.pfsoc.ioscb.ccc", IOSCB_CCC_REG_SIZE);
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memory_region_add_subregion(&s->container, IOSCB_CCC_BASE, &s->ccc);
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memory_region_init_io(&s->pll_mss, OBJECT(s), &mchp_pfsoc_pll_ops, s,
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"mchp.pfsoc.ioscb.pll_mss", IOSCB_SUBMOD_REG_SIZE);
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memory_region_add_subregion(&s->container, IOSCB_PLL_MSS_BASE, &s->pll_mss);
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@ -216,6 +288,8 @@ static void mchp_pfsoc_ioscb_realize(DeviceState *dev, Error **errp)
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IOSCB_SUBMOD_REG_SIZE);
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memory_region_add_subregion(&s->container, IOSCB_IO_CALIB_SGMII_BASE,
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&s->io_calib_sgmii);
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sysbus_init_irq(SYS_BUS_DEVICE(dev), &s->irq);
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}
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static void mchp_pfsoc_ioscb_class_init(ObjectClass *klass, void *data)
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@ -24,10 +24,12 @@
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#include "qemu/bitops.h"
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#include "qemu/log.h"
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#include "qapi/error.h"
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#include "hw/irq.h"
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#include "hw/sysbus.h"
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#include "hw/misc/mchp_pfsoc_sysreg.h"
|
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|
||||
#define ENVM_CR 0xb8
|
||||
#define MESSAGE_INT 0x118c
|
||||
|
||||
static uint64_t mchp_pfsoc_sysreg_read(void *opaque, hwaddr offset,
|
||||
unsigned size)
|
||||
@ -52,10 +54,17 @@ static uint64_t mchp_pfsoc_sysreg_read(void *opaque, hwaddr offset,
|
||||
static void mchp_pfsoc_sysreg_write(void *opaque, hwaddr offset,
|
||||
uint64_t value, unsigned size)
|
||||
{
|
||||
MchpPfSoCSysregState *s = opaque;
|
||||
switch (offset) {
|
||||
case MESSAGE_INT:
|
||||
qemu_irq_lower(s->irq);
|
||||
break;
|
||||
default:
|
||||
qemu_log_mask(LOG_UNIMP, "%s: unimplemented device write "
|
||||
"(size %d, value 0x%" PRIx64
|
||||
", offset 0x%" HWADDR_PRIx ")\n",
|
||||
__func__, size, value, offset);
|
||||
}
|
||||
}
|
||||
|
||||
static const MemoryRegionOps mchp_pfsoc_sysreg_ops = {
|
||||
@ -73,6 +82,7 @@ static void mchp_pfsoc_sysreg_realize(DeviceState *dev, Error **errp)
|
||||
"mchp.pfsoc.sysreg",
|
||||
MCHP_PFSOC_SYSREG_REG_SIZE);
|
||||
sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->sysreg);
|
||||
sysbus_init_irq(SYS_BUS_DEVICE(dev), &s->irq);
|
||||
}
|
||||
|
||||
static void mchp_pfsoc_sysreg_class_init(ObjectClass *klass, void *data)
|
||||
|
||||
@ -4,6 +4,8 @@ config RISCV_NUMA
|
||||
config IBEX
|
||||
bool
|
||||
|
||||
# RISC-V machines in alphabetical order
|
||||
|
||||
config MICROCHIP_PFSOC
|
||||
bool
|
||||
select CADENCE_SDHCI
|
||||
@ -11,7 +13,6 @@ config MICROCHIP_PFSOC
|
||||
select MCHP_PFSOC_IOSCB
|
||||
select MCHP_PFSOC_MMUART
|
||||
select MCHP_PFSOC_SYSREG
|
||||
select MSI_NONBROKEN
|
||||
select RISCV_ACLINT
|
||||
select SIFIVE_PDMA
|
||||
select SIFIVE_PLIC
|
||||
@ -20,14 +21,8 @@ config MICROCHIP_PFSOC
|
||||
config OPENTITAN
|
||||
bool
|
||||
select IBEX
|
||||
select UNIMP
|
||||
|
||||
config SHAKTI_C
|
||||
bool
|
||||
select UNIMP
|
||||
select SHAKTI_UART
|
||||
select RISCV_ACLINT
|
||||
select SIFIVE_PLIC
|
||||
select UNIMP
|
||||
|
||||
config RISCV_VIRT
|
||||
bool
|
||||
@ -37,7 +32,6 @@ config RISCV_VIRT
|
||||
imply TPM_TIS_SYSBUS
|
||||
select RISCV_NUMA
|
||||
select GOLDFISH_RTC
|
||||
select MSI_NONBROKEN
|
||||
select PCI
|
||||
select PCI_EXPRESS_GENERIC_BRIDGE
|
||||
select PFLASH_CFI01
|
||||
@ -51,9 +45,15 @@ config RISCV_VIRT
|
||||
select FW_CFG_DMA
|
||||
select PLATFORM_BUS
|
||||
|
||||
config SHAKTI_C
|
||||
bool
|
||||
select RISCV_ACLINT
|
||||
select SHAKTI_UART
|
||||
select SIFIVE_PLIC
|
||||
select UNIMP
|
||||
|
||||
config SIFIVE_E
|
||||
bool
|
||||
select MSI_NONBROKEN
|
||||
select RISCV_ACLINT
|
||||
select SIFIVE_GPIO
|
||||
select SIFIVE_PLIC
|
||||
@ -64,7 +64,6 @@ config SIFIVE_E
|
||||
config SIFIVE_U
|
||||
bool
|
||||
select CADENCE
|
||||
select MSI_NONBROKEN
|
||||
select RISCV_ACLINT
|
||||
select SIFIVE_GPIO
|
||||
select SIFIVE_PDMA
|
||||
@ -82,6 +81,5 @@ config SPIKE
|
||||
bool
|
||||
select RISCV_NUMA
|
||||
select HTIF
|
||||
select MSI_NONBROKEN
|
||||
select RISCV_ACLINT
|
||||
select SIFIVE_PLIC
|
||||
|
||||
@ -133,11 +133,14 @@ static const MemMapEntry microchip_pfsoc_memmap[] = {
|
||||
[MICROCHIP_PFSOC_USB] = { 0x20201000, 0x1000 },
|
||||
[MICROCHIP_PFSOC_QSPI_XIP] = { 0x21000000, 0x1000000 },
|
||||
[MICROCHIP_PFSOC_IOSCB] = { 0x30000000, 0x10000000 },
|
||||
[MICROCHIP_PFSOC_FABRIC_FIC0] = { 0x2000000000, 0x1000000000 },
|
||||
[MICROCHIP_PFSOC_FABRIC_FIC1] = { 0x3000000000, 0x1000000000 },
|
||||
[MICROCHIP_PFSOC_FABRIC_FIC3] = { 0x40000000, 0x20000000 },
|
||||
[MICROCHIP_PFSOC_DRAM_LO] = { 0x80000000, 0x40000000 },
|
||||
[MICROCHIP_PFSOC_DRAM_LO_ALIAS] = { 0xc0000000, 0x40000000 },
|
||||
[MICROCHIP_PFSOC_DRAM_HI] = { 0x1000000000, 0x0 },
|
||||
[MICROCHIP_PFSOC_DRAM_HI_ALIAS] = { 0x1400000000, 0x0 },
|
||||
|
||||
};
|
||||
|
||||
static void microchip_pfsoc_soc_instance_init(Object *obj)
|
||||
@ -303,6 +306,9 @@ static void microchip_pfsoc_soc_realize(DeviceState *dev, Error **errp)
|
||||
sysbus_realize(SYS_BUS_DEVICE(&s->sysreg), errp);
|
||||
sysbus_mmio_map(SYS_BUS_DEVICE(&s->sysreg), 0,
|
||||
memmap[MICROCHIP_PFSOC_SYSREG].base);
|
||||
sysbus_connect_irq(SYS_BUS_DEVICE(&s->sysreg), 0,
|
||||
qdev_get_gpio_in(DEVICE(s->plic),
|
||||
MICROCHIP_PFSOC_MAILBOX_IRQ));
|
||||
|
||||
/* AXISW */
|
||||
create_unimplemented_device("microchip.pfsoc.axisw",
|
||||
@ -456,11 +462,22 @@ static void microchip_pfsoc_soc_realize(DeviceState *dev, Error **errp)
|
||||
sysbus_realize(SYS_BUS_DEVICE(&s->ioscb), errp);
|
||||
sysbus_mmio_map(SYS_BUS_DEVICE(&s->ioscb), 0,
|
||||
memmap[MICROCHIP_PFSOC_IOSCB].base);
|
||||
sysbus_connect_irq(SYS_BUS_DEVICE(&s->ioscb), 0,
|
||||
qdev_get_gpio_in(DEVICE(s->plic),
|
||||
MICROCHIP_PFSOC_MAILBOX_IRQ));
|
||||
|
||||
/* FPGA Fabric */
|
||||
create_unimplemented_device("microchip.pfsoc.fabricfic3",
|
||||
memmap[MICROCHIP_PFSOC_FABRIC_FIC3].base,
|
||||
memmap[MICROCHIP_PFSOC_FABRIC_FIC3].size);
|
||||
/* FPGA Fabric */
|
||||
create_unimplemented_device("microchip.pfsoc.fabricfic0",
|
||||
memmap[MICROCHIP_PFSOC_FABRIC_FIC0].base,
|
||||
memmap[MICROCHIP_PFSOC_FABRIC_FIC0].size);
|
||||
/* FPGA Fabric */
|
||||
create_unimplemented_device("microchip.pfsoc.fabricfic1",
|
||||
memmap[MICROCHIP_PFSOC_FABRIC_FIC1].base,
|
||||
memmap[MICROCHIP_PFSOC_FABRIC_FIC1].size);
|
||||
|
||||
/* QSPI Flash */
|
||||
memory_region_init_rom(qspi_xip_mem, OBJECT(dev),
|
||||
|
||||
@ -28,6 +28,14 @@
|
||||
#include "qemu/units.h"
|
||||
#include "sysemu/sysemu.h"
|
||||
|
||||
/*
|
||||
* This version of the OpenTitan machine currently supports
|
||||
* OpenTitan RTL version:
|
||||
* <lowRISC/opentitan@d072ac505f82152678d6e04be95c72b728a347b8>
|
||||
*
|
||||
* MMIO mapping as per (specified commit):
|
||||
* lowRISC/opentitan: hw/top_earlgrey/sw/autogen/top_earlgrey_memory.h
|
||||
*/
|
||||
static const MemMapEntry ibex_memmap[] = {
|
||||
[IBEX_DEV_ROM] = { 0x00008000, 0x8000 },
|
||||
[IBEX_DEV_RAM] = { 0x10000000, 0x20000 },
|
||||
@ -38,17 +46,18 @@ static const MemMapEntry ibex_memmap[] = {
|
||||
[IBEX_DEV_I2C] = { 0x40080000, 0x1000 },
|
||||
[IBEX_DEV_PATTGEN] = { 0x400e0000, 0x1000 },
|
||||
[IBEX_DEV_TIMER] = { 0x40100000, 0x1000 },
|
||||
[IBEX_DEV_SENSOR_CTRL] = { 0x40110000, 0x1000 },
|
||||
[IBEX_DEV_OTP_CTRL] = { 0x40130000, 0x4000 },
|
||||
[IBEX_DEV_LC_CTRL] = { 0x40140000, 0x1000 },
|
||||
[IBEX_DEV_USBDEV] = { 0x40150000, 0x1000 },
|
||||
[IBEX_DEV_ALERT_HANDLER] = { 0x40150000, 0x1000 },
|
||||
[IBEX_DEV_SPI_HOST0] = { 0x40300000, 0x1000 },
|
||||
[IBEX_DEV_SPI_HOST1] = { 0x40310000, 0x1000 },
|
||||
[IBEX_DEV_USBDEV] = { 0x40320000, 0x1000 },
|
||||
[IBEX_DEV_PWRMGR] = { 0x40400000, 0x1000 },
|
||||
[IBEX_DEV_RSTMGR] = { 0x40410000, 0x1000 },
|
||||
[IBEX_DEV_CLKMGR] = { 0x40420000, 0x1000 },
|
||||
[IBEX_DEV_PINMUX] = { 0x40460000, 0x1000 },
|
||||
[IBEX_DEV_PADCTRL] = { 0x40470000, 0x1000 },
|
||||
[IBEX_DEV_AON_TIMER] = { 0x40470000, 0x1000 },
|
||||
[IBEX_DEV_SENSOR_CTRL] = { 0x40490000, 0x1000 },
|
||||
[IBEX_DEV_FLASH_CTRL] = { 0x41000000, 0x1000 },
|
||||
[IBEX_DEV_AES] = { 0x41100000, 0x1000 },
|
||||
[IBEX_DEV_HMAC] = { 0x41110000, 0x1000 },
|
||||
@ -59,7 +68,6 @@ static const MemMapEntry ibex_memmap[] = {
|
||||
[IBEX_DEV_ENTROPY] = { 0x41160000, 0x1000 },
|
||||
[IBEX_DEV_EDNO] = { 0x41170000, 0x1000 },
|
||||
[IBEX_DEV_EDN1] = { 0x41180000, 0x1000 },
|
||||
[IBEX_DEV_ALERT_HANDLER] = { 0x411b0000, 0x1000 },
|
||||
[IBEX_DEV_NMI_GEN] = { 0x411c0000, 0x1000 },
|
||||
[IBEX_DEV_PERI] = { 0x411f0000, 0x10000 },
|
||||
[IBEX_DEV_PLIC] = { 0x48000000, 0x4005000 },
|
||||
@ -165,10 +173,8 @@ static void lowrisc_ibex_soc_realize(DeviceState *dev_soc, Error **errp)
|
||||
|
||||
/* PLIC */
|
||||
qdev_prop_set_string(DEVICE(&s->plic), "hart-config", "M");
|
||||
qdev_prop_set_uint32(DEVICE(&s->plic), "hartid-base", 0);
|
||||
qdev_prop_set_uint32(DEVICE(&s->plic), "num-sources", 180);
|
||||
qdev_prop_set_uint32(DEVICE(&s->plic), "num-priorities", 3);
|
||||
qdev_prop_set_uint32(DEVICE(&s->plic), "priority-base", 0x00);
|
||||
qdev_prop_set_uint32(DEVICE(&s->plic), "pending-base", 0x1000);
|
||||
qdev_prop_set_uint32(DEVICE(&s->plic), "enable-base", 0x2000);
|
||||
qdev_prop_set_uint32(DEVICE(&s->plic), "enable-stride", 32);
|
||||
@ -265,8 +271,8 @@ static void lowrisc_ibex_soc_realize(DeviceState *dev_soc, Error **errp)
|
||||
memmap[IBEX_DEV_CLKMGR].base, memmap[IBEX_DEV_CLKMGR].size);
|
||||
create_unimplemented_device("riscv.lowrisc.ibex.pinmux",
|
||||
memmap[IBEX_DEV_PINMUX].base, memmap[IBEX_DEV_PINMUX].size);
|
||||
create_unimplemented_device("riscv.lowrisc.ibex.padctrl",
|
||||
memmap[IBEX_DEV_PADCTRL].base, memmap[IBEX_DEV_PADCTRL].size);
|
||||
create_unimplemented_device("riscv.lowrisc.ibex.aon_timer",
|
||||
memmap[IBEX_DEV_AON_TIMER].base, memmap[IBEX_DEV_AON_TIMER].size);
|
||||
create_unimplemented_device("riscv.lowrisc.ibex.usbdev",
|
||||
memmap[IBEX_DEV_USBDEV].base, memmap[IBEX_DEV_USBDEV].size);
|
||||
create_unimplemented_device("riscv.lowrisc.ibex.flash_ctrl",
|
||||
|
||||
@ -287,7 +287,8 @@ static void create_fdt(SiFiveUState *s, const MemMapEntry *memmap,
|
||||
qemu_fdt_setprop_cells(fdt, nodename, "reg",
|
||||
0x0, memmap[SIFIVE_U_DEV_PLIC].base,
|
||||
0x0, memmap[SIFIVE_U_DEV_PLIC].size);
|
||||
qemu_fdt_setprop_cell(fdt, nodename, "riscv,ndev", 0x35);
|
||||
qemu_fdt_setprop_cell(fdt, nodename, "riscv,ndev",
|
||||
SIFIVE_U_PLIC_NUM_SOURCES - 1);
|
||||
qemu_fdt_setprop_cell(fdt, nodename, "phandle", plic_phandle);
|
||||
plic_phandle = qemu_fdt_get_phandle(fdt, nodename);
|
||||
g_free(cells);
|
||||
|
||||
@ -8,7 +8,6 @@
|
||||
*
|
||||
* 0) HTIF Console and Poweroff
|
||||
* 1) CLINT (Timer and IPI)
|
||||
* 2) PLIC (Platform Level Interrupt Controller)
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms and conditions of the GNU General Public License,
|
||||
|
||||
@ -468,7 +468,8 @@ static void create_fdt_socket_plic(RISCVVirtState *s,
|
||||
plic_cells, s->soc[socket].num_harts * sizeof(uint32_t) * 4);
|
||||
qemu_fdt_setprop_cells(mc->fdt, plic_name, "reg",
|
||||
0x0, plic_addr, 0x0, memmap[VIRT_PLIC].size);
|
||||
qemu_fdt_setprop_cell(mc->fdt, plic_name, "riscv,ndev", VIRTIO_NDEV);
|
||||
qemu_fdt_setprop_cell(mc->fdt, plic_name, "riscv,ndev",
|
||||
VIRT_IRQCHIP_NUM_SOURCES - 1);
|
||||
riscv_socket_fdt_write_id(mc, mc->fdt, plic_name, socket);
|
||||
qemu_fdt_setprop_cell(mc->fdt, plic_name, "phandle",
|
||||
plic_phandles[socket]);
|
||||
@ -546,8 +547,6 @@ static void create_fdt_imsic(RISCVVirtState *s, const MemMapEntry *memmap,
|
||||
riscv_socket_count(mc) * sizeof(uint32_t) * 4);
|
||||
qemu_fdt_setprop_cell(mc->fdt, imsic_name, "riscv,num-ids",
|
||||
VIRT_IRQCHIP_NUM_MSIS);
|
||||
qemu_fdt_setprop_cells(mc->fdt, imsic_name, "riscv,ipi-id",
|
||||
VIRT_IRQCHIP_IPI_MSI);
|
||||
if (riscv_socket_count(mc) > 1) {
|
||||
qemu_fdt_setprop_cell(mc->fdt, imsic_name, "riscv,hart-index-bits",
|
||||
imsic_num_bits(imsic_max_hart_per_socket));
|
||||
@ -597,8 +596,6 @@ static void create_fdt_imsic(RISCVVirtState *s, const MemMapEntry *memmap,
|
||||
riscv_socket_count(mc) * sizeof(uint32_t) * 4);
|
||||
qemu_fdt_setprop_cell(mc->fdt, imsic_name, "riscv,num-ids",
|
||||
VIRT_IRQCHIP_NUM_MSIS);
|
||||
qemu_fdt_setprop_cells(mc->fdt, imsic_name, "riscv,ipi-id",
|
||||
VIRT_IRQCHIP_IPI_MSI);
|
||||
if (imsic_guest_bits) {
|
||||
qemu_fdt_setprop_cell(mc->fdt, imsic_name, "riscv,guest-index-bits",
|
||||
imsic_guest_bits);
|
||||
|
||||
@ -33,7 +33,6 @@ DECLARE_INSTANCE_CHECKER(SiFivePLICState, SIFIVE_PLIC,
|
||||
typedef enum PLICMode {
|
||||
PLICMode_U,
|
||||
PLICMode_S,
|
||||
PLICMode_H,
|
||||
PLICMode_M
|
||||
} PLICMode;
|
||||
|
||||
|
||||
@ -29,7 +29,10 @@ typedef struct MchpPfSoCIoscbState {
|
||||
MemoryRegion lane01;
|
||||
MemoryRegion lane23;
|
||||
MemoryRegion ctrl;
|
||||
MemoryRegion qspixip;
|
||||
MemoryRegion mailbox;
|
||||
MemoryRegion cfg;
|
||||
MemoryRegion ccc;
|
||||
MemoryRegion pll_mss;
|
||||
MemoryRegion cfm_mss;
|
||||
MemoryRegion pll_ddr;
|
||||
@ -40,6 +43,7 @@ typedef struct MchpPfSoCIoscbState {
|
||||
MemoryRegion cfm_sgmii;
|
||||
MemoryRegion bc_sgmii;
|
||||
MemoryRegion io_calib_sgmii;
|
||||
qemu_irq irq;
|
||||
} MchpPfSoCIoscbState;
|
||||
|
||||
#define TYPE_MCHP_PFSOC_IOSCB "mchp.pfsoc.ioscb"
|
||||
|
||||
@ -28,6 +28,7 @@
|
||||
typedef struct MchpPfSoCSysregState {
|
||||
SysBusDevice parent;
|
||||
MemoryRegion sysreg;
|
||||
qemu_irq irq;
|
||||
} MchpPfSoCSysregState;
|
||||
|
||||
#define TYPE_MCHP_PFSOC_SYSREG "mchp.pfsoc.sysreg"
|
||||
|
||||
@ -121,6 +121,8 @@ enum {
|
||||
MICROCHIP_PFSOC_USB,
|
||||
MICROCHIP_PFSOC_QSPI_XIP,
|
||||
MICROCHIP_PFSOC_IOSCB,
|
||||
MICROCHIP_PFSOC_FABRIC_FIC0,
|
||||
MICROCHIP_PFSOC_FABRIC_FIC1,
|
||||
MICROCHIP_PFSOC_FABRIC_FIC3,
|
||||
MICROCHIP_PFSOC_DRAM_LO,
|
||||
MICROCHIP_PFSOC_DRAM_LO_ALIAS,
|
||||
@ -145,14 +147,15 @@ enum {
|
||||
MICROCHIP_PFSOC_MMUART2_IRQ = 92,
|
||||
MICROCHIP_PFSOC_MMUART3_IRQ = 93,
|
||||
MICROCHIP_PFSOC_MMUART4_IRQ = 94,
|
||||
MICROCHIP_PFSOC_MAILBOX_IRQ = 96,
|
||||
};
|
||||
|
||||
#define MICROCHIP_PFSOC_MANAGEMENT_CPU_COUNT 1
|
||||
#define MICROCHIP_PFSOC_COMPUTE_CPU_COUNT 4
|
||||
|
||||
#define MICROCHIP_PFSOC_PLIC_NUM_SOURCES 185
|
||||
#define MICROCHIP_PFSOC_PLIC_NUM_SOURCES 187
|
||||
#define MICROCHIP_PFSOC_PLIC_NUM_PRIORITIES 7
|
||||
#define MICROCHIP_PFSOC_PLIC_PRIORITY_BASE 0x04
|
||||
#define MICROCHIP_PFSOC_PLIC_PRIORITY_BASE 0x00
|
||||
#define MICROCHIP_PFSOC_PLIC_PENDING_BASE 0x1000
|
||||
#define MICROCHIP_PFSOC_PLIC_ENABLE_BASE 0x2000
|
||||
#define MICROCHIP_PFSOC_PLIC_ENABLE_STRIDE 0x80
|
||||
|
||||
@ -81,7 +81,7 @@ enum {
|
||||
IBEX_DEV_RSTMGR,
|
||||
IBEX_DEV_CLKMGR,
|
||||
IBEX_DEV_PINMUX,
|
||||
IBEX_DEV_PADCTRL,
|
||||
IBEX_DEV_AON_TIMER,
|
||||
IBEX_DEV_USBDEV,
|
||||
IBEX_DEV_FLASH_CTRL,
|
||||
IBEX_DEV_PLIC,
|
||||
@ -109,10 +109,10 @@ enum {
|
||||
IBEX_UART0_RX_TIMEOUT_IRQ = 7,
|
||||
IBEX_UART0_RX_PARITY_ERR_IRQ = 8,
|
||||
IBEX_TIMER_TIMEREXPIRED0_0 = 127,
|
||||
IBEX_SPI_HOST0_ERR_IRQ = 151,
|
||||
IBEX_SPI_HOST0_SPI_EVENT_IRQ = 152,
|
||||
IBEX_SPI_HOST1_ERR_IRQ = 153,
|
||||
IBEX_SPI_HOST1_SPI_EVENT_IRQ = 154,
|
||||
IBEX_SPI_HOST0_ERR_IRQ = 134,
|
||||
IBEX_SPI_HOST0_SPI_EVENT_IRQ = 135,
|
||||
IBEX_SPI_HOST1_ERR_IRQ = 136,
|
||||
IBEX_SPI_HOST1_SPI_EVENT_IRQ = 137,
|
||||
};
|
||||
|
||||
#endif
|
||||
|
||||
@ -65,7 +65,7 @@ enum {
|
||||
#define SHAKTI_C_PLIC_NUM_SOURCES 28
|
||||
/* Excluding Priority 0 */
|
||||
#define SHAKTI_C_PLIC_NUM_PRIORITIES 2
|
||||
#define SHAKTI_C_PLIC_PRIORITY_BASE 0x04
|
||||
#define SHAKTI_C_PLIC_PRIORITY_BASE 0x00
|
||||
#define SHAKTI_C_PLIC_PENDING_BASE 0x1000
|
||||
#define SHAKTI_C_PLIC_ENABLE_BASE 0x2000
|
||||
#define SHAKTI_C_PLIC_ENABLE_STRIDE 0x80
|
||||
|
||||
@ -82,9 +82,14 @@ enum {
|
||||
};
|
||||
|
||||
#define SIFIVE_E_PLIC_HART_CONFIG "M"
|
||||
#define SIFIVE_E_PLIC_NUM_SOURCES 127
|
||||
/*
|
||||
* Freedom E310 G002 and G003 supports 52 interrupt sources while
|
||||
* Freedom E310 G000 supports 51 interrupt sources. We use the value
|
||||
* of G002 and G003, so it is 53 (including interrupt source 0).
|
||||
*/
|
||||
#define SIFIVE_E_PLIC_NUM_SOURCES 53
|
||||
#define SIFIVE_E_PLIC_NUM_PRIORITIES 7
|
||||
#define SIFIVE_E_PLIC_PRIORITY_BASE 0x04
|
||||
#define SIFIVE_E_PLIC_PRIORITY_BASE 0x00
|
||||
#define SIFIVE_E_PLIC_PENDING_BASE 0x1000
|
||||
#define SIFIVE_E_PLIC_ENABLE_BASE 0x2000
|
||||
#define SIFIVE_E_PLIC_ENABLE_STRIDE 0x80
|
||||
|
||||
@ -158,7 +158,7 @@ enum {
|
||||
|
||||
#define SIFIVE_U_PLIC_NUM_SOURCES 54
|
||||
#define SIFIVE_U_PLIC_NUM_PRIORITIES 7
|
||||
#define SIFIVE_U_PLIC_PRIORITY_BASE 0x04
|
||||
#define SIFIVE_U_PLIC_PRIORITY_BASE 0x00
|
||||
#define SIFIVE_U_PLIC_PENDING_BASE 0x1000
|
||||
#define SIFIVE_U_PLIC_ENABLE_BASE 0x2000
|
||||
#define SIFIVE_U_PLIC_ENABLE_STRIDE 0x80
|
||||
|
||||
@ -87,20 +87,18 @@ enum {
|
||||
VIRTIO_IRQ = 1, /* 1 to 8 */
|
||||
VIRTIO_COUNT = 8,
|
||||
PCIE_IRQ = 0x20, /* 32 to 35 */
|
||||
VIRT_PLATFORM_BUS_IRQ = 64, /* 64 to 96 */
|
||||
VIRTIO_NDEV = 96 /* Arbitrary maximum number of interrupts */
|
||||
VIRT_PLATFORM_BUS_IRQ = 64, /* 64 to 95 */
|
||||
};
|
||||
|
||||
#define VIRT_PLATFORM_BUS_NUM_IRQS 32
|
||||
|
||||
#define VIRT_IRQCHIP_IPI_MSI 1
|
||||
#define VIRT_IRQCHIP_NUM_MSIS 255
|
||||
#define VIRT_IRQCHIP_NUM_SOURCES VIRTIO_NDEV
|
||||
#define VIRT_IRQCHIP_NUM_SOURCES 96
|
||||
#define VIRT_IRQCHIP_NUM_PRIO_BITS 3
|
||||
#define VIRT_IRQCHIP_MAX_GUESTS_BITS 3
|
||||
#define VIRT_IRQCHIP_MAX_GUESTS ((1U << VIRT_IRQCHIP_MAX_GUESTS_BITS) - 1U)
|
||||
|
||||
#define VIRT_PLIC_PRIORITY_BASE 0x04
|
||||
#define VIRT_PLIC_PRIORITY_BASE 0x00
|
||||
#define VIRT_PLIC_PENDING_BASE 0x1000
|
||||
#define VIRT_PLIC_ENABLE_BASE 0x2000
|
||||
#define VIRT_PLIC_ENABLE_STRIDE 0x80
|
||||
|
||||
@ -76,6 +76,7 @@ static const struct isa_ext_data isa_edata_arr[] = {
|
||||
ISA_EXT_DATA_ENTRY(zicsr, true, PRIV_VERSION_1_10_0, ext_icsr),
|
||||
ISA_EXT_DATA_ENTRY(zifencei, true, PRIV_VERSION_1_10_0, ext_ifencei),
|
||||
ISA_EXT_DATA_ENTRY(zihintpause, true, PRIV_VERSION_1_10_0, ext_zihintpause),
|
||||
ISA_EXT_DATA_ENTRY(zawrs, true, PRIV_VERSION_1_12_0, ext_zawrs),
|
||||
ISA_EXT_DATA_ENTRY(zfh, true, PRIV_VERSION_1_12_0, ext_zfh),
|
||||
ISA_EXT_DATA_ENTRY(zfhmin, true, PRIV_VERSION_1_12_0, ext_zfhmin),
|
||||
ISA_EXT_DATA_ENTRY(zfinx, true, PRIV_VERSION_1_12_0, ext_zfinx),
|
||||
@ -382,6 +383,10 @@ static void riscv_cpu_dump_state(CPUState *cs, FILE *f, int flags)
|
||||
CSR_MHARTID,
|
||||
CSR_MSTATUS,
|
||||
CSR_MSTATUSH,
|
||||
/*
|
||||
* CSR_SSTATUS is intentionally omitted here as its value
|
||||
* can be figured out by looking at CSR_MSTATUS
|
||||
*/
|
||||
CSR_HSTATUS,
|
||||
CSR_VSSTATUS,
|
||||
CSR_MIP,
|
||||
@ -762,6 +767,11 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp)
|
||||
return;
|
||||
}
|
||||
|
||||
if ((cpu->cfg.ext_zawrs) && !cpu->cfg.ext_a) {
|
||||
error_setg(errp, "Zawrs extension requires A extension");
|
||||
return;
|
||||
}
|
||||
|
||||
if ((cpu->cfg.ext_zfh || cpu->cfg.ext_zfhmin) && !cpu->cfg.ext_f) {
|
||||
error_setg(errp, "Zfh/Zfhmin extensions require F extension");
|
||||
return;
|
||||
@ -1017,6 +1027,7 @@ static Property riscv_cpu_extensions[] = {
|
||||
DEFINE_PROP_BOOL("Zifencei", RISCVCPU, cfg.ext_ifencei, true),
|
||||
DEFINE_PROP_BOOL("Zicsr", RISCVCPU, cfg.ext_icsr, true),
|
||||
DEFINE_PROP_BOOL("Zihintpause", RISCVCPU, cfg.ext_zihintpause, true),
|
||||
DEFINE_PROP_BOOL("Zawrs", RISCVCPU, cfg.ext_zawrs, true),
|
||||
DEFINE_PROP_BOOL("Zfh", RISCVCPU, cfg.ext_zfh, false),
|
||||
DEFINE_PROP_BOOL("Zfhmin", RISCVCPU, cfg.ext_zfhmin, false),
|
||||
DEFINE_PROP_BOOL("Zve32f", RISCVCPU, cfg.ext_zve32f, false),
|
||||
|
||||
@ -329,6 +329,9 @@ struct CPUArchState {
|
||||
target_ulong tdata3[RV_MAX_TRIGGERS];
|
||||
struct CPUBreakpoint *cpu_breakpoint[RV_MAX_TRIGGERS];
|
||||
struct CPUWatchpoint *cpu_watchpoint[RV_MAX_TRIGGERS];
|
||||
QEMUTimer *itrigger_timer[RV_MAX_TRIGGERS];
|
||||
int64_t last_icount;
|
||||
bool itrigger_enabled;
|
||||
|
||||
/* machine specific rdtime callback */
|
||||
uint64_t (*rdtime_fn)(void *);
|
||||
@ -366,6 +369,9 @@ struct CPUArchState {
|
||||
|
||||
/* CSRs for execution enviornment configuration */
|
||||
uint64_t menvcfg;
|
||||
uint64_t mstateen[SMSTATEEN_MAX_COUNT];
|
||||
uint64_t hstateen[SMSTATEEN_MAX_COUNT];
|
||||
uint64_t sstateen[SMSTATEEN_MAX_COUNT];
|
||||
target_ulong senvcfg;
|
||||
uint64_t henvcfg;
|
||||
#endif
|
||||
@ -441,11 +447,13 @@ struct RISCVCPUConfig {
|
||||
bool ext_ifencei;
|
||||
bool ext_icsr;
|
||||
bool ext_zihintpause;
|
||||
bool ext_smstateen;
|
||||
bool ext_sstc;
|
||||
bool ext_svinval;
|
||||
bool ext_svnapot;
|
||||
bool ext_svpbmt;
|
||||
bool ext_zdinx;
|
||||
bool ext_zawrs;
|
||||
bool ext_zfh;
|
||||
bool ext_zfhmin;
|
||||
bool ext_zfinx;
|
||||
@ -621,6 +629,8 @@ FIELD(TB_FLAGS, PM_MASK_ENABLED, 22, 1)
|
||||
FIELD(TB_FLAGS, PM_BASE_ENABLED, 23, 1)
|
||||
FIELD(TB_FLAGS, VTA, 24, 1)
|
||||
FIELD(TB_FLAGS, VMA, 25, 1)
|
||||
/* Native debug itrigger */
|
||||
FIELD(TB_FLAGS, ITRIGGER, 26, 1)
|
||||
|
||||
#ifdef TARGET_RISCV32
|
||||
#define riscv_cpu_mxl(env) ((void)(env), MXL_RV32)
|
||||
|
||||
@ -197,6 +197,12 @@
|
||||
/* Supervisor Configuration CSRs */
|
||||
#define CSR_SENVCFG 0x10A
|
||||
|
||||
/* Supervisor state CSRs */
|
||||
#define CSR_SSTATEEN0 0x10C
|
||||
#define CSR_SSTATEEN1 0x10D
|
||||
#define CSR_SSTATEEN2 0x10E
|
||||
#define CSR_SSTATEEN3 0x10F
|
||||
|
||||
/* Supervisor Trap Handling */
|
||||
#define CSR_SSCRATCH 0x140
|
||||
#define CSR_SEPC 0x141
|
||||
@ -244,6 +250,16 @@
|
||||
#define CSR_HENVCFG 0x60A
|
||||
#define CSR_HENVCFGH 0x61A
|
||||
|
||||
/* Hypervisor state CSRs */
|
||||
#define CSR_HSTATEEN0 0x60C
|
||||
#define CSR_HSTATEEN0H 0x61C
|
||||
#define CSR_HSTATEEN1 0x60D
|
||||
#define CSR_HSTATEEN1H 0x61D
|
||||
#define CSR_HSTATEEN2 0x60E
|
||||
#define CSR_HSTATEEN2H 0x61E
|
||||
#define CSR_HSTATEEN3 0x60F
|
||||
#define CSR_HSTATEEN3H 0x61F
|
||||
|
||||
/* Virtual CSRs */
|
||||
#define CSR_VSSTATUS 0x200
|
||||
#define CSR_VSIE 0x204
|
||||
@ -289,6 +305,27 @@
|
||||
#define CSR_MENVCFG 0x30A
|
||||
#define CSR_MENVCFGH 0x31A
|
||||
|
||||
/* Machine state CSRs */
|
||||
#define CSR_MSTATEEN0 0x30C
|
||||
#define CSR_MSTATEEN0H 0x31C
|
||||
#define CSR_MSTATEEN1 0x30D
|
||||
#define CSR_MSTATEEN1H 0x31D
|
||||
#define CSR_MSTATEEN2 0x30E
|
||||
#define CSR_MSTATEEN2H 0x31E
|
||||
#define CSR_MSTATEEN3 0x30F
|
||||
#define CSR_MSTATEEN3H 0x31F
|
||||
|
||||
/* Common defines for all smstateen */
|
||||
#define SMSTATEEN_MAX_COUNT 4
|
||||
#define SMSTATEEN0_CS (1ULL << 0)
|
||||
#define SMSTATEEN0_FCSR (1ULL << 1)
|
||||
#define SMSTATEEN0_HSCONTXT (1ULL << 57)
|
||||
#define SMSTATEEN0_IMSIC (1ULL << 58)
|
||||
#define SMSTATEEN0_AIA (1ULL << 59)
|
||||
#define SMSTATEEN0_SVSLCT (1ULL << 60)
|
||||
#define SMSTATEEN0_HSENVCFG (1ULL << 62)
|
||||
#define SMSTATEEN_STATEEN (1ULL << 63)
|
||||
|
||||
/* Enhanced Physical Memory Protection (ePMP) */
|
||||
#define CSR_MSECCFG 0x747
|
||||
#define CSR_MSECCFGH 0x757
|
||||
|
||||
@ -27,7 +27,9 @@
|
||||
#include "tcg/tcg-op.h"
|
||||
#include "trace.h"
|
||||
#include "semihosting/common-semi.h"
|
||||
#include "sysemu/cpu-timers.h"
|
||||
#include "cpu_bits.h"
|
||||
#include "debug.h"
|
||||
|
||||
int riscv_cpu_mmu_index(CPURISCVState *env, bool ifetch)
|
||||
{
|
||||
@ -103,6 +105,9 @@ void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulong *pc,
|
||||
flags = FIELD_DP32(flags, TB_FLAGS, MSTATUS_HS_VS,
|
||||
get_field(env->mstatus_hs, MSTATUS_VS));
|
||||
}
|
||||
if (riscv_feature(env, RISCV_FEATURE_DEBUG) && !icount_enabled()) {
|
||||
flags = FIELD_DP32(flags, TB_FLAGS, ITRIGGER, env->itrigger_enabled);
|
||||
}
|
||||
#endif
|
||||
|
||||
flags = FIELD_DP32(flags, TB_FLAGS, XL, env->xl);
|
||||
@ -662,6 +667,9 @@ void riscv_cpu_set_mode(CPURISCVState *env, target_ulong newpriv)
|
||||
if (newpriv == PRV_H) {
|
||||
newpriv = PRV_U;
|
||||
}
|
||||
if (icount_enabled() && newpriv != env->priv) {
|
||||
riscv_itrigger_update_priv(env);
|
||||
}
|
||||
/* tlb_flush is unnecessary as mode is contained in mmu_idx */
|
||||
env->priv = newpriv;
|
||||
env->xl = cpu_recompute_xl(env);
|
||||
@ -698,24 +706,26 @@ static int get_physical_address_pmp(CPURISCVState *env, int *prot,
|
||||
int mode)
|
||||
{
|
||||
pmp_priv_t pmp_priv;
|
||||
target_ulong tlb_size_pmp = 0;
|
||||
int pmp_index = -1;
|
||||
|
||||
if (!riscv_feature(env, RISCV_FEATURE_PMP)) {
|
||||
*prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
|
||||
return TRANSLATE_SUCCESS;
|
||||
}
|
||||
|
||||
if (!pmp_hart_has_privs(env, addr, size, 1 << access_type, &pmp_priv,
|
||||
mode)) {
|
||||
pmp_index = pmp_hart_has_privs(env, addr, size, 1 << access_type,
|
||||
&pmp_priv, mode);
|
||||
if (pmp_index < 0) {
|
||||
*prot = 0;
|
||||
return TRANSLATE_PMP_FAIL;
|
||||
}
|
||||
|
||||
*prot = pmp_priv_to_page_prot(pmp_priv);
|
||||
if (tlb_size != NULL) {
|
||||
if (pmp_is_range_in_tlb(env, addr & ~(*tlb_size - 1), &tlb_size_pmp)) {
|
||||
*tlb_size = tlb_size_pmp;
|
||||
}
|
||||
if ((tlb_size != NULL) && pmp_index != MAX_RISCV_PMPS) {
|
||||
target_ulong tlb_sa = addr & ~(TARGET_PAGE_SIZE - 1);
|
||||
target_ulong tlb_ea = tlb_sa + TARGET_PAGE_SIZE - 1;
|
||||
|
||||
*tlb_size = pmp_get_tlb_size(env, pmp_index, tlb_sa, tlb_ea);
|
||||
}
|
||||
|
||||
return TRANSLATE_SUCCESS;
|
||||
@ -1240,6 +1250,7 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
|
||||
}
|
||||
}
|
||||
|
||||
pmu_tlb_fill_incr_ctr(cpu, access_type);
|
||||
if (riscv_cpu_virt_enabled(env) ||
|
||||
((riscv_cpu_two_stage_lookup(mmu_idx) || two_stage_lookup) &&
|
||||
access_type != MMU_INST_FETCH)) {
|
||||
@ -1303,7 +1314,6 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
|
||||
}
|
||||
}
|
||||
} else {
|
||||
pmu_tlb_fill_incr_ctr(cpu, access_type);
|
||||
/* Single stage lookup */
|
||||
ret = get_physical_address(env, &pa, &prot, address, NULL,
|
||||
access_type, mmu_idx, true, false, false);
|
||||
|
||||
@ -41,6 +41,42 @@ void riscv_set_csr_ops(int csrno, riscv_csr_operations *ops)
|
||||
}
|
||||
|
||||
/* Predicates */
|
||||
#if !defined(CONFIG_USER_ONLY)
|
||||
static RISCVException smstateen_acc_ok(CPURISCVState *env, int index,
|
||||
uint64_t bit)
|
||||
{
|
||||
bool virt = riscv_cpu_virt_enabled(env);
|
||||
CPUState *cs = env_cpu(env);
|
||||
RISCVCPU *cpu = RISCV_CPU(cs);
|
||||
|
||||
if (env->priv == PRV_M || !cpu->cfg.ext_smstateen) {
|
||||
return RISCV_EXCP_NONE;
|
||||
}
|
||||
|
||||
if (!(env->mstateen[index] & bit)) {
|
||||
return RISCV_EXCP_ILLEGAL_INST;
|
||||
}
|
||||
|
||||
if (virt) {
|
||||
if (!(env->hstateen[index] & bit)) {
|
||||
return RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
|
||||
}
|
||||
|
||||
if (env->priv == PRV_U && !(env->sstateen[index] & bit)) {
|
||||
return RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
|
||||
}
|
||||
}
|
||||
|
||||
if (env->priv == PRV_U && riscv_has_ext(env, RVS)) {
|
||||
if (!(env->sstateen[index] & bit)) {
|
||||
return RISCV_EXCP_ILLEGAL_INST;
|
||||
}
|
||||
}
|
||||
|
||||
return RISCV_EXCP_NONE;
|
||||
}
|
||||
#endif
|
||||
|
||||
static RISCVException fs(CPURISCVState *env, int csrno)
|
||||
{
|
||||
#if !defined(CONFIG_USER_ONLY)
|
||||
@ -283,6 +319,72 @@ static RISCVException umode32(CPURISCVState *env, int csrno)
|
||||
return umode(env, csrno);
|
||||
}
|
||||
|
||||
static RISCVException mstateen(CPURISCVState *env, int csrno)
|
||||
{
|
||||
CPUState *cs = env_cpu(env);
|
||||
RISCVCPU *cpu = RISCV_CPU(cs);
|
||||
|
||||
if (!cpu->cfg.ext_smstateen) {
|
||||
return RISCV_EXCP_ILLEGAL_INST;
|
||||
}
|
||||
|
||||
return any(env, csrno);
|
||||
}
|
||||
|
||||
static RISCVException hstateen_pred(CPURISCVState *env, int csrno, int base)
|
||||
{
|
||||
CPUState *cs = env_cpu(env);
|
||||
RISCVCPU *cpu = RISCV_CPU(cs);
|
||||
|
||||
if (!cpu->cfg.ext_smstateen) {
|
||||
return RISCV_EXCP_ILLEGAL_INST;
|
||||
}
|
||||
|
||||
if (env->priv < PRV_M) {
|
||||
if (!(env->mstateen[csrno - base] & SMSTATEEN_STATEEN)) {
|
||||
return RISCV_EXCP_ILLEGAL_INST;
|
||||
}
|
||||
}
|
||||
|
||||
return hmode(env, csrno);
|
||||
}
|
||||
|
||||
static RISCVException hstateen(CPURISCVState *env, int csrno)
|
||||
{
|
||||
return hstateen_pred(env, csrno, CSR_HSTATEEN0);
|
||||
}
|
||||
|
||||
static RISCVException hstateenh(CPURISCVState *env, int csrno)
|
||||
{
|
||||
return hstateen_pred(env, csrno, CSR_HSTATEEN0H);
|
||||
}
|
||||
|
||||
static RISCVException sstateen(CPURISCVState *env, int csrno)
|
||||
{
|
||||
bool virt = riscv_cpu_virt_enabled(env);
|
||||
int index = csrno - CSR_SSTATEEN0;
|
||||
CPUState *cs = env_cpu(env);
|
||||
RISCVCPU *cpu = RISCV_CPU(cs);
|
||||
|
||||
if (!cpu->cfg.ext_smstateen) {
|
||||
return RISCV_EXCP_ILLEGAL_INST;
|
||||
}
|
||||
|
||||
if (env->priv < PRV_M) {
|
||||
if (!(env->mstateen[index] & SMSTATEEN_STATEEN)) {
|
||||
return RISCV_EXCP_ILLEGAL_INST;
|
||||
}
|
||||
|
||||
if (virt) {
|
||||
if (!(env->hstateen[index] & SMSTATEEN_STATEEN)) {
|
||||
return RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
return smode(env, csrno);
|
||||
}
|
||||
|
||||
/* Checks if PointerMasking registers could be accessed */
|
||||
static RISCVException pointer_masking(CPURISCVState *env, int csrno)
|
||||
{
|
||||
@ -838,7 +940,7 @@ static RISCVException sstc(CPURISCVState *env, int csrno)
|
||||
}
|
||||
|
||||
if (riscv_cpu_virt_enabled(env)) {
|
||||
if (!(get_field(env->hcounteren, COUNTEREN_TM) &
|
||||
if (!(get_field(env->hcounteren, COUNTEREN_TM) &&
|
||||
get_field(env->henvcfg, HENVCFG_STCE))) {
|
||||
return RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
|
||||
}
|
||||
@ -1808,6 +1910,13 @@ static RISCVException write_menvcfgh(CPURISCVState *env, int csrno,
|
||||
static RISCVException read_senvcfg(CPURISCVState *env, int csrno,
|
||||
target_ulong *val)
|
||||
{
|
||||
RISCVException ret;
|
||||
|
||||
ret = smstateen_acc_ok(env, 0, SMSTATEEN0_HSENVCFG);
|
||||
if (ret != RISCV_EXCP_NONE) {
|
||||
return ret;
|
||||
}
|
||||
|
||||
*val = env->senvcfg;
|
||||
return RISCV_EXCP_NONE;
|
||||
}
|
||||
@ -1816,15 +1925,27 @@ static RISCVException write_senvcfg(CPURISCVState *env, int csrno,
|
||||
target_ulong val)
|
||||
{
|
||||
uint64_t mask = SENVCFG_FIOM | SENVCFG_CBIE | SENVCFG_CBCFE | SENVCFG_CBZE;
|
||||
RISCVException ret;
|
||||
|
||||
ret = smstateen_acc_ok(env, 0, SMSTATEEN0_HSENVCFG);
|
||||
if (ret != RISCV_EXCP_NONE) {
|
||||
return ret;
|
||||
}
|
||||
|
||||
env->senvcfg = (env->senvcfg & ~mask) | (val & mask);
|
||||
|
||||
return RISCV_EXCP_NONE;
|
||||
}
|
||||
|
||||
static RISCVException read_henvcfg(CPURISCVState *env, int csrno,
|
||||
target_ulong *val)
|
||||
{
|
||||
RISCVException ret;
|
||||
|
||||
ret = smstateen_acc_ok(env, 0, SMSTATEEN0_HSENVCFG);
|
||||
if (ret != RISCV_EXCP_NONE) {
|
||||
return ret;
|
||||
}
|
||||
|
||||
*val = env->henvcfg;
|
||||
return RISCV_EXCP_NONE;
|
||||
}
|
||||
@ -1833,6 +1954,12 @@ static RISCVException write_henvcfg(CPURISCVState *env, int csrno,
|
||||
target_ulong val)
|
||||
{
|
||||
uint64_t mask = HENVCFG_FIOM | HENVCFG_CBIE | HENVCFG_CBCFE | HENVCFG_CBZE;
|
||||
RISCVException ret;
|
||||
|
||||
ret = smstateen_acc_ok(env, 0, SMSTATEEN0_HSENVCFG);
|
||||
if (ret != RISCV_EXCP_NONE) {
|
||||
return ret;
|
||||
}
|
||||
|
||||
if (riscv_cpu_mxl(env) == MXL_RV64) {
|
||||
mask |= HENVCFG_PBMTE | HENVCFG_STCE;
|
||||
@ -1846,6 +1973,13 @@ static RISCVException write_henvcfg(CPURISCVState *env, int csrno,
|
||||
static RISCVException read_henvcfgh(CPURISCVState *env, int csrno,
|
||||
target_ulong *val)
|
||||
{
|
||||
RISCVException ret;
|
||||
|
||||
ret = smstateen_acc_ok(env, 0, SMSTATEEN0_HSENVCFG);
|
||||
if (ret != RISCV_EXCP_NONE) {
|
||||
return ret;
|
||||
}
|
||||
|
||||
*val = env->henvcfg >> 32;
|
||||
return RISCV_EXCP_NONE;
|
||||
}
|
||||
@ -1855,12 +1989,208 @@ static RISCVException write_henvcfgh(CPURISCVState *env, int csrno,
|
||||
{
|
||||
uint64_t mask = HENVCFG_PBMTE | HENVCFG_STCE;
|
||||
uint64_t valh = (uint64_t)val << 32;
|
||||
RISCVException ret;
|
||||
|
||||
ret = smstateen_acc_ok(env, 0, SMSTATEEN0_HSENVCFG);
|
||||
if (ret != RISCV_EXCP_NONE) {
|
||||
return ret;
|
||||
}
|
||||
|
||||
env->henvcfg = (env->henvcfg & ~mask) | (valh & mask);
|
||||
return RISCV_EXCP_NONE;
|
||||
}
|
||||
|
||||
static RISCVException read_mstateen(CPURISCVState *env, int csrno,
|
||||
target_ulong *val)
|
||||
{
|
||||
*val = env->mstateen[csrno - CSR_MSTATEEN0];
|
||||
|
||||
return RISCV_EXCP_NONE;
|
||||
}
|
||||
|
||||
static RISCVException write_mstateen(CPURISCVState *env, int csrno,
|
||||
uint64_t wr_mask, target_ulong new_val)
|
||||
{
|
||||
uint64_t *reg;
|
||||
|
||||
reg = &env->mstateen[csrno - CSR_MSTATEEN0];
|
||||
*reg = (*reg & ~wr_mask) | (new_val & wr_mask);
|
||||
|
||||
return RISCV_EXCP_NONE;
|
||||
}
|
||||
|
||||
static RISCVException write_mstateen0(CPURISCVState *env, int csrno,
|
||||
target_ulong new_val)
|
||||
{
|
||||
uint64_t wr_mask = SMSTATEEN_STATEEN | SMSTATEEN0_HSENVCFG;
|
||||
|
||||
return write_mstateen(env, csrno, wr_mask, new_val);
|
||||
}
|
||||
|
||||
static RISCVException write_mstateen_1_3(CPURISCVState *env, int csrno,
|
||||
target_ulong new_val)
|
||||
{
|
||||
return write_mstateen(env, csrno, SMSTATEEN_STATEEN, new_val);
|
||||
}
|
||||
|
||||
static RISCVException read_mstateenh(CPURISCVState *env, int csrno,
|
||||
target_ulong *val)
|
||||
{
|
||||
*val = env->mstateen[csrno - CSR_MSTATEEN0H] >> 32;
|
||||
|
||||
return RISCV_EXCP_NONE;
|
||||
}
|
||||
|
||||
static RISCVException write_mstateenh(CPURISCVState *env, int csrno,
|
||||
uint64_t wr_mask, target_ulong new_val)
|
||||
{
|
||||
uint64_t *reg, val;
|
||||
|
||||
reg = &env->mstateen[csrno - CSR_MSTATEEN0H];
|
||||
val = (uint64_t)new_val << 32;
|
||||
val |= *reg & 0xFFFFFFFF;
|
||||
*reg = (*reg & ~wr_mask) | (val & wr_mask);
|
||||
|
||||
return RISCV_EXCP_NONE;
|
||||
}
|
||||
|
||||
static RISCVException write_mstateen0h(CPURISCVState *env, int csrno,
|
||||
target_ulong new_val)
|
||||
{
|
||||
uint64_t wr_mask = SMSTATEEN_STATEEN | SMSTATEEN0_HSENVCFG;
|
||||
|
||||
return write_mstateenh(env, csrno, wr_mask, new_val);
|
||||
}
|
||||
|
||||
static RISCVException write_mstateenh_1_3(CPURISCVState *env, int csrno,
|
||||
target_ulong new_val)
|
||||
{
|
||||
return write_mstateenh(env, csrno, SMSTATEEN_STATEEN, new_val);
|
||||
}
|
||||
|
||||
static RISCVException read_hstateen(CPURISCVState *env, int csrno,
|
||||
target_ulong *val)
|
||||
{
|
||||
int index = csrno - CSR_HSTATEEN0;
|
||||
|
||||
*val = env->hstateen[index] & env->mstateen[index];
|
||||
|
||||
return RISCV_EXCP_NONE;
|
||||
}
|
||||
|
||||
static RISCVException write_hstateen(CPURISCVState *env, int csrno,
|
||||
uint64_t mask, target_ulong new_val)
|
||||
{
|
||||
int index = csrno - CSR_HSTATEEN0;
|
||||
uint64_t *reg, wr_mask;
|
||||
|
||||
reg = &env->hstateen[index];
|
||||
wr_mask = env->mstateen[index] & mask;
|
||||
*reg = (*reg & ~wr_mask) | (new_val & wr_mask);
|
||||
|
||||
return RISCV_EXCP_NONE;
|
||||
}
|
||||
|
||||
static RISCVException write_hstateen0(CPURISCVState *env, int csrno,
|
||||
target_ulong new_val)
|
||||
{
|
||||
uint64_t wr_mask = SMSTATEEN_STATEEN | SMSTATEEN0_HSENVCFG;
|
||||
|
||||
return write_hstateen(env, csrno, wr_mask, new_val);
|
||||
}
|
||||
|
||||
static RISCVException write_hstateen_1_3(CPURISCVState *env, int csrno,
|
||||
target_ulong new_val)
|
||||
{
|
||||
return write_hstateen(env, csrno, SMSTATEEN_STATEEN, new_val);
|
||||
}
|
||||
|
||||
static RISCVException read_hstateenh(CPURISCVState *env, int csrno,
|
||||
target_ulong *val)
|
||||
{
|
||||
int index = csrno - CSR_HSTATEEN0H;
|
||||
|
||||
*val = (env->hstateen[index] >> 32) & (env->mstateen[index] >> 32);
|
||||
|
||||
return RISCV_EXCP_NONE;
|
||||
}
|
||||
|
||||
static RISCVException write_hstateenh(CPURISCVState *env, int csrno,
|
||||
uint64_t mask, target_ulong new_val)
|
||||
{
|
||||
int index = csrno - CSR_HSTATEEN0H;
|
||||
uint64_t *reg, wr_mask, val;
|
||||
|
||||
reg = &env->hstateen[index];
|
||||
val = (uint64_t)new_val << 32;
|
||||
val |= *reg & 0xFFFFFFFF;
|
||||
wr_mask = env->mstateen[index] & mask;
|
||||
*reg = (*reg & ~wr_mask) | (val & wr_mask);
|
||||
|
||||
return RISCV_EXCP_NONE;
|
||||
}
|
||||
|
||||
static RISCVException write_hstateen0h(CPURISCVState *env, int csrno,
|
||||
target_ulong new_val)
|
||||
{
|
||||
uint64_t wr_mask = SMSTATEEN_STATEEN | SMSTATEEN0_HSENVCFG;
|
||||
|
||||
return write_hstateenh(env, csrno, wr_mask, new_val);
|
||||
}
|
||||
|
||||
static RISCVException write_hstateenh_1_3(CPURISCVState *env, int csrno,
|
||||
target_ulong new_val)
|
||||
{
|
||||
return write_hstateenh(env, csrno, SMSTATEEN_STATEEN, new_val);
|
||||
}
|
||||
|
||||
static RISCVException read_sstateen(CPURISCVState *env, int csrno,
|
||||
target_ulong *val)
|
||||
{
|
||||
bool virt = riscv_cpu_virt_enabled(env);
|
||||
int index = csrno - CSR_SSTATEEN0;
|
||||
|
||||
*val = env->sstateen[index] & env->mstateen[index];
|
||||
if (virt) {
|
||||
*val &= env->hstateen[index];
|
||||
}
|
||||
|
||||
return RISCV_EXCP_NONE;
|
||||
}
|
||||
|
||||
static RISCVException write_sstateen(CPURISCVState *env, int csrno,
|
||||
uint64_t mask, target_ulong new_val)
|
||||
{
|
||||
bool virt = riscv_cpu_virt_enabled(env);
|
||||
int index = csrno - CSR_SSTATEEN0;
|
||||
uint64_t wr_mask;
|
||||
uint64_t *reg;
|
||||
|
||||
wr_mask = env->mstateen[index] & mask;
|
||||
if (virt) {
|
||||
wr_mask &= env->hstateen[index];
|
||||
}
|
||||
|
||||
reg = &env->sstateen[index];
|
||||
*reg = (*reg & ~wr_mask) | (new_val & wr_mask);
|
||||
|
||||
return RISCV_EXCP_NONE;
|
||||
}
|
||||
|
||||
static RISCVException write_sstateen0(CPURISCVState *env, int csrno,
|
||||
target_ulong new_val)
|
||||
{
|
||||
uint64_t wr_mask = SMSTATEEN_STATEEN | SMSTATEEN0_HSENVCFG;
|
||||
|
||||
return write_sstateen(env, csrno, wr_mask, new_val);
|
||||
}
|
||||
|
||||
static RISCVException write_sstateen_1_3(CPURISCVState *env, int csrno,
|
||||
target_ulong new_val)
|
||||
{
|
||||
return write_sstateen(env, csrno, SMSTATEEN_STATEEN, new_val);
|
||||
}
|
||||
|
||||
static RISCVException rmw_mip64(CPURISCVState *env, int csrno,
|
||||
uint64_t *ret_val,
|
||||
uint64_t new_val, uint64_t wr_mask)
|
||||
@ -3744,6 +4074,65 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
|
||||
[CSR_HENVCFGH] = { "henvcfgh", hmode32, read_henvcfgh, write_henvcfgh,
|
||||
.min_priv_ver = PRIV_VERSION_1_12_0 },
|
||||
|
||||
/* Smstateen extension CSRs */
|
||||
[CSR_MSTATEEN0] = { "mstateen0", mstateen, read_mstateen, write_mstateen0,
|
||||
.min_priv_ver = PRIV_VERSION_1_12_0 },
|
||||
[CSR_MSTATEEN0H] = { "mstateen0h", mstateen, read_mstateenh,
|
||||
write_mstateen0h,
|
||||
.min_priv_ver = PRIV_VERSION_1_12_0 },
|
||||
[CSR_MSTATEEN1] = { "mstateen1", mstateen, read_mstateen,
|
||||
write_mstateen_1_3,
|
||||
.min_priv_ver = PRIV_VERSION_1_12_0 },
|
||||
[CSR_MSTATEEN1H] = { "mstateen1h", mstateen, read_mstateenh,
|
||||
write_mstateenh_1_3,
|
||||
.min_priv_ver = PRIV_VERSION_1_12_0 },
|
||||
[CSR_MSTATEEN2] = { "mstateen2", mstateen, read_mstateen,
|
||||
write_mstateen_1_3,
|
||||
.min_priv_ver = PRIV_VERSION_1_12_0 },
|
||||
[CSR_MSTATEEN2H] = { "mstateen2h", mstateen, read_mstateenh,
|
||||
write_mstateenh_1_3,
|
||||
.min_priv_ver = PRIV_VERSION_1_12_0 },
|
||||
[CSR_MSTATEEN3] = { "mstateen3", mstateen, read_mstateen,
|
||||
write_mstateen_1_3,
|
||||
.min_priv_ver = PRIV_VERSION_1_12_0 },
|
||||
[CSR_MSTATEEN3H] = { "mstateen3h", mstateen, read_mstateenh,
|
||||
write_mstateenh_1_3,
|
||||
.min_priv_ver = PRIV_VERSION_1_12_0 },
|
||||
[CSR_HSTATEEN0] = { "hstateen0", hstateen, read_hstateen, write_hstateen0,
|
||||
.min_priv_ver = PRIV_VERSION_1_12_0 },
|
||||
[CSR_HSTATEEN0H] = { "hstateen0h", hstateenh, read_hstateenh,
|
||||
write_hstateen0h,
|
||||
.min_priv_ver = PRIV_VERSION_1_12_0 },
|
||||
[CSR_HSTATEEN1] = { "hstateen1", hstateen, read_hstateen,
|
||||
write_hstateen_1_3,
|
||||
.min_priv_ver = PRIV_VERSION_1_12_0 },
|
||||
[CSR_HSTATEEN1H] = { "hstateen1h", hstateenh, read_hstateenh,
|
||||
write_hstateenh_1_3,
|
||||
.min_priv_ver = PRIV_VERSION_1_12_0 },
|
||||
[CSR_HSTATEEN2] = { "hstateen2", hstateen, read_hstateen,
|
||||
write_hstateen_1_3,
|
||||
.min_priv_ver = PRIV_VERSION_1_12_0 },
|
||||
[CSR_HSTATEEN2H] = { "hstateen2h", hstateenh, read_hstateenh,
|
||||
write_hstateenh_1_3,
|
||||
.min_priv_ver = PRIV_VERSION_1_12_0 },
|
||||
[CSR_HSTATEEN3] = { "hstateen3", hstateen, read_hstateen,
|
||||
write_hstateen_1_3,
|
||||
.min_priv_ver = PRIV_VERSION_1_12_0 },
|
||||
[CSR_HSTATEEN3H] = { "hstateen3h", hstateenh, read_hstateenh,
|
||||
write_hstateenh_1_3,
|
||||
.min_priv_ver = PRIV_VERSION_1_12_0 },
|
||||
[CSR_SSTATEEN0] = { "sstateen0", sstateen, read_sstateen, write_sstateen0,
|
||||
.min_priv_ver = PRIV_VERSION_1_12_0 },
|
||||
[CSR_SSTATEEN1] = { "sstateen1", sstateen, read_sstateen,
|
||||
write_sstateen_1_3,
|
||||
.min_priv_ver = PRIV_VERSION_1_12_0 },
|
||||
[CSR_SSTATEEN2] = { "sstateen2", sstateen, read_sstateen,
|
||||
write_sstateen_1_3,
|
||||
.min_priv_ver = PRIV_VERSION_1_12_0 },
|
||||
[CSR_SSTATEEN3] = { "sstateen3", sstateen, read_sstateen,
|
||||
write_sstateen_1_3,
|
||||
.min_priv_ver = PRIV_VERSION_1_12_0 },
|
||||
|
||||
/* Supervisor Trap Setup */
|
||||
[CSR_SSTATUS] = { "sstatus", smode, read_sstatus, write_sstatus,
|
||||
NULL, read_sstatus_i128 },
|
||||
|
||||
@ -29,6 +29,8 @@
|
||||
#include "cpu.h"
|
||||
#include "trace.h"
|
||||
#include "exec/exec-all.h"
|
||||
#include "exec/helper-proto.h"
|
||||
#include "sysemu/cpu-timers.h"
|
||||
|
||||
/*
|
||||
* The following M-mode trigger CSRs are implemented:
|
||||
@ -496,10 +498,209 @@ static void type6_reg_write(CPURISCVState *env, target_ulong index,
|
||||
return;
|
||||
}
|
||||
|
||||
target_ulong tdata_csr_read(CPURISCVState *env, int tdata_index)
|
||||
/* icount trigger type */
|
||||
static inline int
|
||||
itrigger_get_count(CPURISCVState *env, int index)
|
||||
{
|
||||
return get_field(env->tdata1[index], ITRIGGER_COUNT);
|
||||
}
|
||||
|
||||
static inline void
|
||||
itrigger_set_count(CPURISCVState *env, int index, int value)
|
||||
{
|
||||
env->tdata1[index] = set_field(env->tdata1[index],
|
||||
ITRIGGER_COUNT, value);
|
||||
}
|
||||
|
||||
static bool check_itrigger_priv(CPURISCVState *env, int index)
|
||||
{
|
||||
target_ulong tdata1 = env->tdata1[index];
|
||||
if (riscv_cpu_virt_enabled(env)) {
|
||||
/* check VU/VS bit against current privilege level */
|
||||
return (get_field(tdata1, ITRIGGER_VS) == env->priv) ||
|
||||
(get_field(tdata1, ITRIGGER_VU) == env->priv);
|
||||
} else {
|
||||
/* check U/S/M bit against current privilege level */
|
||||
return (get_field(tdata1, ITRIGGER_M) == env->priv) ||
|
||||
(get_field(tdata1, ITRIGGER_S) == env->priv) ||
|
||||
(get_field(tdata1, ITRIGGER_U) == env->priv);
|
||||
}
|
||||
}
|
||||
|
||||
bool riscv_itrigger_enabled(CPURISCVState *env)
|
||||
{
|
||||
int count;
|
||||
for (int i = 0; i < RV_MAX_TRIGGERS; i++) {
|
||||
if (get_trigger_type(env, i) != TRIGGER_TYPE_INST_CNT) {
|
||||
continue;
|
||||
}
|
||||
if (check_itrigger_priv(env, i)) {
|
||||
continue;
|
||||
}
|
||||
count = itrigger_get_count(env, i);
|
||||
if (!count) {
|
||||
continue;
|
||||
}
|
||||
return true;
|
||||
}
|
||||
|
||||
return false;
|
||||
}
|
||||
|
||||
void helper_itrigger_match(CPURISCVState *env)
|
||||
{
|
||||
int count;
|
||||
for (int i = 0; i < RV_MAX_TRIGGERS; i++) {
|
||||
if (get_trigger_type(env, i) != TRIGGER_TYPE_INST_CNT) {
|
||||
continue;
|
||||
}
|
||||
if (check_itrigger_priv(env, i)) {
|
||||
continue;
|
||||
}
|
||||
count = itrigger_get_count(env, i);
|
||||
if (!count) {
|
||||
continue;
|
||||
}
|
||||
itrigger_set_count(env, i, count--);
|
||||
if (!count) {
|
||||
env->itrigger_enabled = riscv_itrigger_enabled(env);
|
||||
do_trigger_action(env, i);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
static void riscv_itrigger_update_count(CPURISCVState *env)
|
||||
{
|
||||
int count, executed;
|
||||
/*
|
||||
* Record last icount, so that we can evaluate the executed instructions
|
||||
* since last priviledge mode change or timer expire.
|
||||
*/
|
||||
int64_t last_icount = env->last_icount, current_icount;
|
||||
current_icount = env->last_icount = icount_get_raw();
|
||||
|
||||
for (int i = 0; i < RV_MAX_TRIGGERS; i++) {
|
||||
if (get_trigger_type(env, i) != TRIGGER_TYPE_INST_CNT) {
|
||||
continue;
|
||||
}
|
||||
count = itrigger_get_count(env, i);
|
||||
if (!count) {
|
||||
continue;
|
||||
}
|
||||
/*
|
||||
* Only when priviledge is changed or itrigger timer expires,
|
||||
* the count field in itrigger tdata1 register is updated.
|
||||
* And the count field in itrigger only contains remaining value.
|
||||
*/
|
||||
if (check_itrigger_priv(env, i)) {
|
||||
/*
|
||||
* If itrigger enabled in this priviledge mode, the number of
|
||||
* executed instructions since last priviledge change
|
||||
* should be reduced from current itrigger count.
|
||||
*/
|
||||
executed = current_icount - last_icount;
|
||||
itrigger_set_count(env, i, count - executed);
|
||||
if (count == executed) {
|
||||
do_trigger_action(env, i);
|
||||
}
|
||||
} else {
|
||||
/*
|
||||
* If itrigger is not enabled in this priviledge mode,
|
||||
* the number of executed instructions will be discard and
|
||||
* the count field in itrigger will not change.
|
||||
*/
|
||||
timer_mod(env->itrigger_timer[i],
|
||||
current_icount + count);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
static void riscv_itrigger_timer_cb(void *opaque)
|
||||
{
|
||||
riscv_itrigger_update_count((CPURISCVState *)opaque);
|
||||
}
|
||||
|
||||
void riscv_itrigger_update_priv(CPURISCVState *env)
|
||||
{
|
||||
riscv_itrigger_update_count(env);
|
||||
}
|
||||
|
||||
static target_ulong itrigger_validate(CPURISCVState *env,
|
||||
target_ulong ctrl)
|
||||
{
|
||||
target_ulong val;
|
||||
|
||||
/* validate the generic part first */
|
||||
val = tdata1_validate(env, ctrl, TRIGGER_TYPE_INST_CNT);
|
||||
|
||||
/* validate unimplemented (always zero) bits */
|
||||
warn_always_zero_bit(ctrl, ITRIGGER_ACTION, "action");
|
||||
warn_always_zero_bit(ctrl, ITRIGGER_HIT, "hit");
|
||||
warn_always_zero_bit(ctrl, ITRIGGER_PENDING, "pending");
|
||||
|
||||
/* keep the mode and attribute bits */
|
||||
val |= ctrl & (ITRIGGER_VU | ITRIGGER_VS | ITRIGGER_U | ITRIGGER_S |
|
||||
ITRIGGER_M | ITRIGGER_COUNT);
|
||||
|
||||
return val;
|
||||
}
|
||||
|
||||
static void itrigger_reg_write(CPURISCVState *env, target_ulong index,
|
||||
int tdata_index, target_ulong val)
|
||||
{
|
||||
target_ulong new_val;
|
||||
|
||||
switch (tdata_index) {
|
||||
case TDATA1:
|
||||
/* set timer for icount */
|
||||
new_val = itrigger_validate(env, val);
|
||||
if (new_val != env->tdata1[index]) {
|
||||
env->tdata1[index] = new_val;
|
||||
if (icount_enabled()) {
|
||||
env->last_icount = icount_get_raw();
|
||||
/* set the count to timer */
|
||||
timer_mod(env->itrigger_timer[index],
|
||||
env->last_icount + itrigger_get_count(env, index));
|
||||
} else {
|
||||
env->itrigger_enabled = riscv_itrigger_enabled(env);
|
||||
}
|
||||
}
|
||||
break;
|
||||
case TDATA2:
|
||||
qemu_log_mask(LOG_UNIMP,
|
||||
"tdata2 is not supported for icount trigger\n");
|
||||
break;
|
||||
case TDATA3:
|
||||
qemu_log_mask(LOG_UNIMP,
|
||||
"tdata3 is not supported for icount trigger\n");
|
||||
break;
|
||||
default:
|
||||
g_assert_not_reached();
|
||||
}
|
||||
|
||||
return;
|
||||
}
|
||||
|
||||
static int itrigger_get_adjust_count(CPURISCVState *env)
|
||||
{
|
||||
int count = itrigger_get_count(env, env->trigger_cur), executed;
|
||||
if ((count != 0) && check_itrigger_priv(env, env->trigger_cur)) {
|
||||
executed = icount_get_raw() - env->last_icount;
|
||||
count += executed;
|
||||
}
|
||||
return count;
|
||||
}
|
||||
|
||||
target_ulong tdata_csr_read(CPURISCVState *env, int tdata_index)
|
||||
{
|
||||
int trigger_type;
|
||||
switch (tdata_index) {
|
||||
case TDATA1:
|
||||
trigger_type = extract_trigger_type(env, env->tdata1[env->trigger_cur]);
|
||||
if ((trigger_type == TRIGGER_TYPE_INST_CNT) && icount_enabled()) {
|
||||
return deposit64(env->tdata1[env->trigger_cur], 10, 14,
|
||||
itrigger_get_adjust_count(env));
|
||||
}
|
||||
return env->tdata1[env->trigger_cur];
|
||||
case TDATA2:
|
||||
return env->tdata2[env->trigger_cur];
|
||||
@ -528,6 +729,8 @@ void tdata_csr_write(CPURISCVState *env, int tdata_index, target_ulong val)
|
||||
type6_reg_write(env, env->trigger_cur, tdata_index, val);
|
||||
break;
|
||||
case TRIGGER_TYPE_INST_CNT:
|
||||
itrigger_reg_write(env, env->trigger_cur, tdata_index, val);
|
||||
break;
|
||||
case TRIGGER_TYPE_INT:
|
||||
case TRIGGER_TYPE_EXCP:
|
||||
case TRIGGER_TYPE_EXT_SRC:
|
||||
@ -725,5 +928,7 @@ void riscv_trigger_init(CPURISCVState *env)
|
||||
env->tdata3[i] = 0;
|
||||
env->cpu_breakpoint[i] = NULL;
|
||||
env->cpu_watchpoint[i] = NULL;
|
||||
env->itrigger_timer[i] = timer_new_ns(QEMU_CLOCK_VIRTUAL,
|
||||
riscv_itrigger_timer_cb, env);
|
||||
}
|
||||
}
|
||||
|
||||
@ -118,6 +118,17 @@ enum {
|
||||
SIZE_NUM = 16
|
||||
};
|
||||
|
||||
/* itrigger filed masks */
|
||||
#define ITRIGGER_ACTION 0x3f
|
||||
#define ITRIGGER_U BIT(6)
|
||||
#define ITRIGGER_S BIT(7)
|
||||
#define ITRIGGER_PENDING BIT(8)
|
||||
#define ITRIGGER_M BIT(9)
|
||||
#define ITRIGGER_COUNT (0x3fff << 10)
|
||||
#define ITRIGGER_HIT BIT(24)
|
||||
#define ITRIGGER_VU BIT(25)
|
||||
#define ITRIGGER_VS BIT(26)
|
||||
|
||||
bool tdata_available(CPURISCVState *env, int tdata_index);
|
||||
|
||||
target_ulong tselect_csr_read(CPURISCVState *env);
|
||||
@ -134,4 +145,6 @@ bool riscv_cpu_debug_check_watchpoint(CPUState *cs, CPUWatchpoint *wp);
|
||||
|
||||
void riscv_trigger_init(CPURISCVState *env);
|
||||
|
||||
bool riscv_itrigger_enabled(CPURISCVState *env);
|
||||
void riscv_itrigger_update_priv(CPURISCVState *env);
|
||||
#endif /* RISCV_DEBUG_H */
|
||||
|
||||
@ -109,6 +109,8 @@ DEF_HELPER_1(sret, tl, env)
|
||||
DEF_HELPER_1(mret, tl, env)
|
||||
DEF_HELPER_1(wfi, void, env)
|
||||
DEF_HELPER_1(tlb_flush, void, env)
|
||||
/* Native Debug */
|
||||
DEF_HELPER_1(itrigger_match, void, env)
|
||||
#endif
|
||||
|
||||
/* Hypervisor functions */
|
||||
|
||||
@ -718,6 +718,10 @@ vsetvli 0 ........... ..... 111 ..... 1010111 @r2_zimm11
|
||||
vsetivli 11 .......... ..... 111 ..... 1010111 @r2_zimm10
|
||||
vsetvl 1000000 ..... ..... 111 ..... 1010111 @r
|
||||
|
||||
# *** Zawrs Standard Extension ***
|
||||
wrs_nto 000000001101 00000 000 00000 1110011
|
||||
wrs_sto 000000011101 00000 000 00000 1110011
|
||||
|
||||
# *** RV32 Zba Standard Extension ***
|
||||
sh1add 0010000 .......... 010 ..... 0110011 @r
|
||||
sh2add 0010000 .......... 100 ..... 0110011 @r
|
||||
|
||||
@ -78,7 +78,7 @@ static bool trans_sret(DisasContext *ctx, arg_sret *a)
|
||||
if (has_ext(ctx, RVS)) {
|
||||
decode_save_opc(ctx);
|
||||
gen_helper_sret(cpu_pc, cpu_env);
|
||||
tcg_gen_exit_tb(NULL, 0); /* no chaining */
|
||||
exit_tb(ctx); /* no chaining */
|
||||
ctx->base.is_jmp = DISAS_NORETURN;
|
||||
} else {
|
||||
return false;
|
||||
@ -94,7 +94,7 @@ static bool trans_mret(DisasContext *ctx, arg_mret *a)
|
||||
#ifndef CONFIG_USER_ONLY
|
||||
decode_save_opc(ctx);
|
||||
gen_helper_mret(cpu_pc, cpu_env);
|
||||
tcg_gen_exit_tb(NULL, 0); /* no chaining */
|
||||
exit_tb(ctx); /* no chaining */
|
||||
ctx->base.is_jmp = DISAS_NORETURN;
|
||||
return true;
|
||||
#else
|
||||
|
||||
@ -66,7 +66,7 @@ static bool trans_jalr(DisasContext *ctx, arg_jalr *a)
|
||||
}
|
||||
|
||||
gen_set_gpri(ctx, a->rd, ctx->pc_succ_insn);
|
||||
tcg_gen_lookup_and_goto_ptr();
|
||||
lookup_and_goto_ptr(ctx);
|
||||
|
||||
if (misaligned) {
|
||||
gen_set_label(misaligned);
|
||||
@ -803,7 +803,7 @@ static bool trans_pause(DisasContext *ctx, arg_pause *a)
|
||||
* end the TB and return to main loop
|
||||
*/
|
||||
gen_set_pc_imm(ctx, ctx->pc_succ_insn);
|
||||
tcg_gen_exit_tb(NULL, 0);
|
||||
exit_tb(ctx);
|
||||
ctx->base.is_jmp = DISAS_NORETURN;
|
||||
|
||||
return true;
|
||||
@ -827,7 +827,7 @@ static bool trans_fence_i(DisasContext *ctx, arg_fence_i *a)
|
||||
* however we need to end the translation block
|
||||
*/
|
||||
gen_set_pc_imm(ctx, ctx->pc_succ_insn);
|
||||
tcg_gen_exit_tb(NULL, 0);
|
||||
exit_tb(ctx);
|
||||
ctx->base.is_jmp = DISAS_NORETURN;
|
||||
return true;
|
||||
}
|
||||
@ -838,7 +838,7 @@ static bool do_csr_post(DisasContext *ctx)
|
||||
decode_save_opc(ctx);
|
||||
/* We may have changed important cpu state -- exit to main loop. */
|
||||
gen_set_pc_imm(ctx, ctx->pc_succ_insn);
|
||||
tcg_gen_exit_tb(NULL, 0);
|
||||
exit_tb(ctx);
|
||||
ctx->base.is_jmp = DISAS_NORETURN;
|
||||
return true;
|
||||
}
|
||||
|
||||
@ -196,7 +196,7 @@ static bool do_vsetvl(DisasContext *s, int rd, int rs1, TCGv s2)
|
||||
mark_vs_dirty(s);
|
||||
|
||||
gen_set_pc_imm(s, s->pc_succ_insn);
|
||||
tcg_gen_lookup_and_goto_ptr();
|
||||
lookup_and_goto_ptr(s);
|
||||
s->base.is_jmp = DISAS_NORETURN;
|
||||
|
||||
if (rd == 0 && rs1 == 0) {
|
||||
@ -222,7 +222,7 @@ static bool do_vsetivli(DisasContext *s, int rd, TCGv s1, TCGv s2)
|
||||
gen_set_gpr(s, rd, dst);
|
||||
mark_vs_dirty(s);
|
||||
gen_set_pc_imm(s, s->pc_succ_insn);
|
||||
tcg_gen_lookup_and_goto_ptr();
|
||||
lookup_and_goto_ptr(s);
|
||||
s->base.is_jmp = DISAS_NORETURN;
|
||||
|
||||
return true;
|
||||
|
||||
51
target/riscv/insn_trans/trans_rvzawrs.c.inc
Normal file
51
target/riscv/insn_trans/trans_rvzawrs.c.inc
Normal file
@ -0,0 +1,51 @@
|
||||
/*
|
||||
* RISC-V translation routines for the RISC-V Zawrs Extension.
|
||||
*
|
||||
* Copyright (c) 2022 Christoph Muellner, christoph.muellner@vrull.io
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms and conditions of the GNU General Public License,
|
||||
* version 2 or later, as published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along with
|
||||
* this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
*/
|
||||
|
||||
static bool trans_wrs(DisasContext *ctx)
|
||||
{
|
||||
if (!ctx->cfg_ptr->ext_zawrs) {
|
||||
return false;
|
||||
}
|
||||
|
||||
/*
|
||||
* The specification says:
|
||||
* While stalled, an implementation is permitted to occasionally
|
||||
* terminate the stall and complete execution for any reason.
|
||||
*
|
||||
* So let's just exit TB and return to the main loop.
|
||||
*/
|
||||
|
||||
/* Clear the load reservation (if any). */
|
||||
tcg_gen_movi_tl(load_res, -1);
|
||||
|
||||
gen_set_pc_imm(ctx, ctx->pc_succ_insn);
|
||||
tcg_gen_exit_tb(NULL, 0);
|
||||
ctx->base.is_jmp = DISAS_NORETURN;
|
||||
|
||||
return true;
|
||||
}
|
||||
|
||||
#define GEN_TRANS_WRS(insn) \
|
||||
static bool trans_ ## insn(DisasContext *ctx, arg_ ## insn *a) \
|
||||
{ \
|
||||
(void)a; \
|
||||
return trans_wrs(ctx); \
|
||||
}
|
||||
|
||||
GEN_TRANS_WRS(wrs_nto)
|
||||
GEN_TRANS_WRS(wrs_sto)
|
||||
@ -21,6 +21,8 @@
|
||||
#include "qemu/error-report.h"
|
||||
#include "sysemu/kvm.h"
|
||||
#include "migration/cpu.h"
|
||||
#include "sysemu/cpu-timers.h"
|
||||
#include "debug.h"
|
||||
|
||||
static bool pmp_needed(void *opaque)
|
||||
{
|
||||
@ -229,11 +231,24 @@ static bool debug_needed(void *opaque)
|
||||
return riscv_feature(env, RISCV_FEATURE_DEBUG);
|
||||
}
|
||||
|
||||
static int debug_post_load(void *opaque, int version_id)
|
||||
{
|
||||
RISCVCPU *cpu = opaque;
|
||||
CPURISCVState *env = &cpu->env;
|
||||
|
||||
if (icount_enabled()) {
|
||||
env->itrigger_enabled = riscv_itrigger_enabled(env);
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const VMStateDescription vmstate_debug = {
|
||||
.name = "cpu/debug",
|
||||
.version_id = 2,
|
||||
.minimum_version_id = 2,
|
||||
.needed = debug_needed,
|
||||
.post_load = debug_post_load,
|
||||
.fields = (VMStateField[]) {
|
||||
VMSTATE_UINTTL(env.trigger_cur, RISCVCPU),
|
||||
VMSTATE_UINTTL_ARRAY(env.tdata1, RISCVCPU, RV_MAX_TRIGGERS),
|
||||
@ -253,6 +268,26 @@ static int riscv_cpu_post_load(void *opaque, int version_id)
|
||||
return 0;
|
||||
}
|
||||
|
||||
static bool smstateen_needed(void *opaque)
|
||||
{
|
||||
RISCVCPU *cpu = opaque;
|
||||
|
||||
return cpu->cfg.ext_smstateen;
|
||||
}
|
||||
|
||||
static const VMStateDescription vmstate_smstateen = {
|
||||
.name = "cpu/smtateen",
|
||||
.version_id = 1,
|
||||
.minimum_version_id = 1,
|
||||
.needed = smstateen_needed,
|
||||
.fields = (VMStateField[]) {
|
||||
VMSTATE_UINT64_ARRAY(env.mstateen, RISCVCPU, 4),
|
||||
VMSTATE_UINT64_ARRAY(env.hstateen, RISCVCPU, 4),
|
||||
VMSTATE_UINT64_ARRAY(env.sstateen, RISCVCPU, 4),
|
||||
VMSTATE_END_OF_LIST()
|
||||
}
|
||||
};
|
||||
|
||||
static bool envcfg_needed(void *opaque)
|
||||
{
|
||||
RISCVCPU *cpu = opaque;
|
||||
@ -364,6 +399,7 @@ const VMStateDescription vmstate_riscv_cpu = {
|
||||
&vmstate_kvmtimer,
|
||||
&vmstate_envcfg,
|
||||
&vmstate_debug,
|
||||
&vmstate_smstateen,
|
||||
NULL
|
||||
}
|
||||
};
|
||||
|
||||
@ -149,21 +149,24 @@ target_ulong helper_sret(CPURISCVState *env)
|
||||
}
|
||||
|
||||
mstatus = env->mstatus;
|
||||
prev_priv = get_field(mstatus, MSTATUS_SPP);
|
||||
mstatus = set_field(mstatus, MSTATUS_SIE,
|
||||
get_field(mstatus, MSTATUS_SPIE));
|
||||
mstatus = set_field(mstatus, MSTATUS_SPIE, 1);
|
||||
mstatus = set_field(mstatus, MSTATUS_SPP, PRV_U);
|
||||
if (env->priv_ver >= PRIV_VERSION_1_12_0) {
|
||||
mstatus = set_field(mstatus, MSTATUS_MPRV, 0);
|
||||
}
|
||||
env->mstatus = mstatus;
|
||||
|
||||
if (riscv_has_ext(env, RVH) && !riscv_cpu_virt_enabled(env)) {
|
||||
/* We support Hypervisor extensions and virtulisation is disabled */
|
||||
target_ulong hstatus = env->hstatus;
|
||||
|
||||
prev_priv = get_field(mstatus, MSTATUS_SPP);
|
||||
prev_virt = get_field(hstatus, HSTATUS_SPV);
|
||||
|
||||
hstatus = set_field(hstatus, HSTATUS_SPV, 0);
|
||||
mstatus = set_field(mstatus, MSTATUS_SPP, 0);
|
||||
mstatus = set_field(mstatus, SSTATUS_SIE,
|
||||
get_field(mstatus, SSTATUS_SPIE));
|
||||
mstatus = set_field(mstatus, SSTATUS_SPIE, 1);
|
||||
|
||||
env->mstatus = mstatus;
|
||||
env->hstatus = hstatus;
|
||||
|
||||
if (prev_virt) {
|
||||
@ -171,14 +174,6 @@ target_ulong helper_sret(CPURISCVState *env)
|
||||
}
|
||||
|
||||
riscv_cpu_set_virt_enabled(env, prev_virt);
|
||||
} else {
|
||||
prev_priv = get_field(mstatus, MSTATUS_SPP);
|
||||
|
||||
mstatus = set_field(mstatus, MSTATUS_SIE,
|
||||
get_field(mstatus, MSTATUS_SPIE));
|
||||
mstatus = set_field(mstatus, MSTATUS_SPIE, 1);
|
||||
mstatus = set_field(mstatus, MSTATUS_SPP, PRV_U);
|
||||
env->mstatus = mstatus;
|
||||
}
|
||||
|
||||
riscv_cpu_set_mode(env, prev_priv);
|
||||
@ -202,7 +197,7 @@ target_ulong helper_mret(CPURISCVState *env)
|
||||
|
||||
if (riscv_feature(env, RISCV_FEATURE_PMP) &&
|
||||
!pmp_get_num_rules(env) && (prev_priv != PRV_M)) {
|
||||
riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
|
||||
riscv_raise_exception(env, RISCV_EXCP_INST_ACCESS_FAULT, GETPC());
|
||||
}
|
||||
|
||||
target_ulong prev_virt = get_field(env->mstatus, MSTATUS_MPV);
|
||||
@ -211,6 +206,9 @@ target_ulong helper_mret(CPURISCVState *env)
|
||||
mstatus = set_field(mstatus, MSTATUS_MPIE, 1);
|
||||
mstatus = set_field(mstatus, MSTATUS_MPP, PRV_U);
|
||||
mstatus = set_field(mstatus, MSTATUS_MPV, 0);
|
||||
if ((env->priv_ver >= PRIV_VERSION_1_12_0) && (prev_priv != PRV_M)) {
|
||||
mstatus = set_field(mstatus, MSTATUS_MPRV, 0);
|
||||
}
|
||||
env->mstatus = mstatus;
|
||||
riscv_cpu_set_mode(env, prev_priv);
|
||||
|
||||
|
||||
@ -292,8 +292,11 @@ static bool pmp_hart_has_privs_default(CPURISCVState *env, target_ulong addr,
|
||||
|
||||
/*
|
||||
* Check if the address has required RWX privs to complete desired operation
|
||||
* Return PMP rule index if a pmp rule match
|
||||
* Return MAX_RISCV_PMPS if default match
|
||||
* Return negtive value if no match
|
||||
*/
|
||||
bool pmp_hart_has_privs(CPURISCVState *env, target_ulong addr,
|
||||
int pmp_hart_has_privs(CPURISCVState *env, target_ulong addr,
|
||||
target_ulong size, pmp_priv_t privs, pmp_priv_t *allowed_privs,
|
||||
target_ulong mode)
|
||||
{
|
||||
@ -305,8 +308,10 @@ bool pmp_hart_has_privs(CPURISCVState *env, target_ulong addr,
|
||||
|
||||
/* Short cut if no rules */
|
||||
if (0 == pmp_get_num_rules(env)) {
|
||||
return pmp_hart_has_privs_default(env, addr, size, privs,
|
||||
allowed_privs, mode);
|
||||
if (pmp_hart_has_privs_default(env, addr, size, privs,
|
||||
allowed_privs, mode)) {
|
||||
ret = MAX_RISCV_PMPS;
|
||||
}
|
||||
}
|
||||
|
||||
if (size == 0) {
|
||||
@ -333,7 +338,7 @@ bool pmp_hart_has_privs(CPURISCVState *env, target_ulong addr,
|
||||
if ((s + e) == 1) {
|
||||
qemu_log_mask(LOG_GUEST_ERROR,
|
||||
"pmp violation - access is partially inside\n");
|
||||
ret = 0;
|
||||
ret = -1;
|
||||
break;
|
||||
}
|
||||
|
||||
@ -436,18 +441,22 @@ bool pmp_hart_has_privs(CPURISCVState *env, target_ulong addr,
|
||||
}
|
||||
}
|
||||
|
||||
ret = ((privs & *allowed_privs) == privs);
|
||||
if ((privs & *allowed_privs) == privs) {
|
||||
ret = i;
|
||||
}
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
/* No rule matched */
|
||||
if (ret == -1) {
|
||||
return pmp_hart_has_privs_default(env, addr, size, privs,
|
||||
allowed_privs, mode);
|
||||
if (pmp_hart_has_privs_default(env, addr, size, privs,
|
||||
allowed_privs, mode)) {
|
||||
ret = MAX_RISCV_PMPS;
|
||||
}
|
||||
}
|
||||
|
||||
return ret == 1 ? true : false;
|
||||
return ret;
|
||||
}
|
||||
|
||||
/*
|
||||
@ -586,48 +595,15 @@ target_ulong mseccfg_csr_read(CPURISCVState *env)
|
||||
* Calculate the TLB size if the start address or the end address of
|
||||
* PMP entry is presented in the TLB page.
|
||||
*/
|
||||
static target_ulong pmp_get_tlb_size(CPURISCVState *env, int pmp_index,
|
||||
target_ulong pmp_get_tlb_size(CPURISCVState *env, int pmp_index,
|
||||
target_ulong tlb_sa, target_ulong tlb_ea)
|
||||
{
|
||||
target_ulong pmp_sa = env->pmp_state.addr[pmp_index].sa;
|
||||
target_ulong pmp_ea = env->pmp_state.addr[pmp_index].ea;
|
||||
|
||||
if (pmp_sa >= tlb_sa && pmp_ea <= tlb_ea) {
|
||||
return pmp_ea - pmp_sa + 1;
|
||||
}
|
||||
|
||||
if (pmp_sa >= tlb_sa && pmp_sa <= tlb_ea && pmp_ea >= tlb_ea) {
|
||||
return tlb_ea - pmp_sa + 1;
|
||||
}
|
||||
|
||||
if (pmp_ea <= tlb_ea && pmp_ea >= tlb_sa && pmp_sa <= tlb_sa) {
|
||||
return pmp_ea - tlb_sa + 1;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/*
|
||||
* Check is there a PMP entry which range covers this page. If so,
|
||||
* try to find the minimum granularity for the TLB size.
|
||||
*/
|
||||
bool pmp_is_range_in_tlb(CPURISCVState *env, hwaddr tlb_sa,
|
||||
target_ulong *tlb_size)
|
||||
{
|
||||
int i;
|
||||
target_ulong val;
|
||||
target_ulong tlb_ea = (tlb_sa + TARGET_PAGE_SIZE - 1);
|
||||
|
||||
for (i = 0; i < MAX_RISCV_PMPS; i++) {
|
||||
val = pmp_get_tlb_size(env, i, tlb_sa, tlb_ea);
|
||||
if (val) {
|
||||
if (*tlb_size == 0 || *tlb_size > val) {
|
||||
*tlb_size = val;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
if (*tlb_size != 0) {
|
||||
if (pmp_sa <= tlb_sa && pmp_ea >= tlb_ea) {
|
||||
return TARGET_PAGE_SIZE;
|
||||
} else {
|
||||
/*
|
||||
* At this point we have a tlb_size that is the smallest possible size
|
||||
* That fits within a TARGET_PAGE_SIZE and the PMP region.
|
||||
@ -636,14 +612,8 @@ bool pmp_is_range_in_tlb(CPURISCVState *env, hwaddr tlb_sa,
|
||||
* This means the result isn't cached in the TLB and is only used for
|
||||
* a single translation.
|
||||
*/
|
||||
if (*tlb_size < TARGET_PAGE_SIZE) {
|
||||
*tlb_size = 1;
|
||||
return 1;
|
||||
}
|
||||
|
||||
return true;
|
||||
}
|
||||
|
||||
return false;
|
||||
}
|
||||
|
||||
/*
|
||||
|
||||
@ -72,11 +72,11 @@ target_ulong mseccfg_csr_read(CPURISCVState *env);
|
||||
void pmpaddr_csr_write(CPURISCVState *env, uint32_t addr_index,
|
||||
target_ulong val);
|
||||
target_ulong pmpaddr_csr_read(CPURISCVState *env, uint32_t addr_index);
|
||||
bool pmp_hart_has_privs(CPURISCVState *env, target_ulong addr,
|
||||
int pmp_hart_has_privs(CPURISCVState *env, target_ulong addr,
|
||||
target_ulong size, pmp_priv_t privs, pmp_priv_t *allowed_privs,
|
||||
target_ulong mode);
|
||||
bool pmp_is_range_in_tlb(CPURISCVState *env, hwaddr tlb_sa,
|
||||
target_ulong *tlb_size);
|
||||
target_ulong pmp_get_tlb_size(CPURISCVState *env, int pmp_index,
|
||||
target_ulong tlb_sa, target_ulong tlb_ea);
|
||||
void pmp_update_rule_addr(CPURISCVState *env, uint32_t pmp_index);
|
||||
void pmp_update_rule_nums(CPURISCVState *env);
|
||||
uint32_t pmp_get_num_rules(CPURISCVState *env);
|
||||
|
||||
@ -76,6 +76,7 @@ typedef struct DisasContext {
|
||||
to reset this known value. */
|
||||
int frm;
|
||||
RISCVMXL ol;
|
||||
bool virt_inst_excp;
|
||||
bool virt_enabled;
|
||||
const RISCVCPUConfig *cfg_ptr;
|
||||
bool hlsx;
|
||||
@ -111,6 +112,8 @@ typedef struct DisasContext {
|
||||
/* PointerMasking extension */
|
||||
bool pm_mask_enabled;
|
||||
bool pm_base_enabled;
|
||||
/* Use icount trigger for native debug */
|
||||
bool itrigger;
|
||||
/* TCG of the current insn_start */
|
||||
TCGOp *insn_start;
|
||||
} DisasContext;
|
||||
@ -243,7 +246,11 @@ static void gen_exception_illegal(DisasContext *ctx)
|
||||
{
|
||||
tcg_gen_st_i32(tcg_constant_i32(ctx->opcode), cpu_env,
|
||||
offsetof(CPURISCVState, bins));
|
||||
if (ctx->virt_inst_excp) {
|
||||
generate_exception(ctx, RISCV_EXCP_VIRT_INSTRUCTION_FAULT);
|
||||
} else {
|
||||
generate_exception(ctx, RISCV_EXCP_ILLEGAL_INST);
|
||||
}
|
||||
}
|
||||
|
||||
static void gen_exception_inst_addr_mis(DisasContext *ctx)
|
||||
@ -252,15 +259,39 @@ static void gen_exception_inst_addr_mis(DisasContext *ctx)
|
||||
generate_exception(ctx, RISCV_EXCP_INST_ADDR_MIS);
|
||||
}
|
||||
|
||||
static void lookup_and_goto_ptr(DisasContext *ctx)
|
||||
{
|
||||
#ifndef CONFIG_USER_ONLY
|
||||
if (ctx->itrigger) {
|
||||
gen_helper_itrigger_match(cpu_env);
|
||||
}
|
||||
#endif
|
||||
tcg_gen_lookup_and_goto_ptr();
|
||||
}
|
||||
|
||||
static void exit_tb(DisasContext *ctx)
|
||||
{
|
||||
#ifndef CONFIG_USER_ONLY
|
||||
if (ctx->itrigger) {
|
||||
gen_helper_itrigger_match(cpu_env);
|
||||
}
|
||||
#endif
|
||||
tcg_gen_exit_tb(NULL, 0);
|
||||
}
|
||||
|
||||
static void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest)
|
||||
{
|
||||
if (translator_use_goto_tb(&ctx->base, dest)) {
|
||||
/*
|
||||
* Under itrigger, instruction executes one by one like singlestep,
|
||||
* direct block chain benefits will be small.
|
||||
*/
|
||||
if (translator_use_goto_tb(&ctx->base, dest) && !ctx->itrigger) {
|
||||
tcg_gen_goto_tb(n);
|
||||
gen_set_pc_imm(ctx, dest);
|
||||
tcg_gen_exit_tb(ctx->base.tb, n);
|
||||
} else {
|
||||
gen_set_pc_imm(ctx, dest);
|
||||
tcg_gen_lookup_and_goto_ptr();
|
||||
lookup_and_goto_ptr(ctx);
|
||||
}
|
||||
}
|
||||
|
||||
@ -1029,6 +1060,7 @@ static uint32_t opcode_at(DisasContextBase *dcbase, target_ulong pc)
|
||||
#include "insn_trans/trans_rvh.c.inc"
|
||||
#include "insn_trans/trans_rvv.c.inc"
|
||||
#include "insn_trans/trans_rvb.c.inc"
|
||||
#include "insn_trans/trans_rvzawrs.c.inc"
|
||||
#include "insn_trans/trans_rvzfh.c.inc"
|
||||
#include "insn_trans/trans_rvk.c.inc"
|
||||
#include "insn_trans/trans_privileged.c.inc"
|
||||
@ -1062,17 +1094,14 @@ static void decode_opc(CPURISCVState *env, DisasContext *ctx, uint16_t opcode)
|
||||
{ has_XVentanaCondOps_p, decode_XVentanaCodeOps },
|
||||
};
|
||||
|
||||
ctx->virt_inst_excp = false;
|
||||
/* Check for compressed insn */
|
||||
if (insn_len(opcode) == 2) {
|
||||
if (!has_ext(ctx, RVC)) {
|
||||
gen_exception_illegal(ctx);
|
||||
} else {
|
||||
ctx->opcode = opcode;
|
||||
ctx->pc_succ_insn = ctx->base.pc_next + 2;
|
||||
if (decode_insn16(ctx, opcode)) {
|
||||
if (has_ext(ctx, RVC) && decode_insn16(ctx, opcode)) {
|
||||
return;
|
||||
}
|
||||
}
|
||||
} else {
|
||||
uint32_t opcode32 = opcode;
|
||||
opcode32 = deposit32(opcode32, 16, 16,
|
||||
@ -1136,6 +1165,7 @@ static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
|
||||
memset(ctx->ftemp, 0, sizeof(ctx->ftemp));
|
||||
ctx->pm_mask_enabled = FIELD_EX32(tb_flags, TB_FLAGS, PM_MASK_ENABLED);
|
||||
ctx->pm_base_enabled = FIELD_EX32(tb_flags, TB_FLAGS, PM_BASE_ENABLED);
|
||||
ctx->itrigger = FIELD_EX32(tb_flags, TB_FLAGS, ITRIGGER);
|
||||
ctx->zero = tcg_constant_tl(0);
|
||||
}
|
||||
|
||||
@ -1175,7 +1205,7 @@ static void riscv_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu)
|
||||
|
||||
/* Only the first insn within a TB is allowed to cross a page boundary. */
|
||||
if (ctx->base.is_jmp == DISAS_NEXT) {
|
||||
if (!is_same_page(&ctx->base, ctx->base.pc_next)) {
|
||||
if (ctx->itrigger || !is_same_page(&ctx->base, ctx->base.pc_next)) {
|
||||
ctx->base.is_jmp = DISAS_TOO_MANY;
|
||||
} else {
|
||||
unsigned page_ofs = ctx->base.pc_next & ~TARGET_PAGE_MASK;
|
||||
|
||||
@ -154,13 +154,26 @@ static bool tcg_target_const_match(int64_t val, TCGType type, int ct)
|
||||
if ((ct & TCG_CT_CONST_ZERO) && val == 0) {
|
||||
return 1;
|
||||
}
|
||||
if ((ct & TCG_CT_CONST_S12) && val == sextreg(val, 0, 12)) {
|
||||
/*
|
||||
* Sign extended from 12 bits: [-0x800, 0x7ff].
|
||||
* Used for most arithmetic, as this is the isa field.
|
||||
*/
|
||||
if ((ct & TCG_CT_CONST_S12) && val >= -0x800 && val <= 0x7ff) {
|
||||
return 1;
|
||||
}
|
||||
if ((ct & TCG_CT_CONST_N12) && -val == sextreg(-val, 0, 12)) {
|
||||
/*
|
||||
* Sign extended from 12 bits, negated: [-0x7ff, 0x800].
|
||||
* Used for subtraction, where a constant must be handled by ADDI.
|
||||
*/
|
||||
if ((ct & TCG_CT_CONST_N12) && val >= -0x7ff && val <= 0x800) {
|
||||
return 1;
|
||||
}
|
||||
if ((ct & TCG_CT_CONST_M12) && val >= -0xfff && val <= 0xfff) {
|
||||
/*
|
||||
* Sign extended from 12 bits, +/- matching: [-0x7ff, 0x7ff].
|
||||
* Used by addsub2, which may need the negative operation,
|
||||
* and requires the modified constant to be representable.
|
||||
*/
|
||||
if ((ct & TCG_CT_CONST_M12) && val >= -0x7ff && val <= 0x7ff) {
|
||||
return 1;
|
||||
}
|
||||
return 0;
|
||||
@ -687,9 +700,15 @@ static void tcg_out_addsub2(TCGContext *s,
|
||||
if (cbl) {
|
||||
tcg_out_opc_imm(s, opc_addi, rl, al, bl);
|
||||
tcg_out_opc_imm(s, OPC_SLTIU, TCG_REG_TMP0, rl, bl);
|
||||
} else if (rl == al && rl == bl) {
|
||||
} else if (al == bl) {
|
||||
/*
|
||||
* If the input regs overlap, this is a simple doubling
|
||||
* and carry-out is the input msb. This special case is
|
||||
* required when the output reg overlaps the input,
|
||||
* but we might as well use it always.
|
||||
*/
|
||||
tcg_out_opc_imm(s, OPC_SLTI, TCG_REG_TMP0, al, 0);
|
||||
tcg_out_opc_reg(s, opc_addi, rl, al, bl);
|
||||
tcg_out_opc_reg(s, opc_add, rl, al, al);
|
||||
} else {
|
||||
tcg_out_opc_reg(s, opc_add, rl, al, bl);
|
||||
tcg_out_opc_reg(s, OPC_SLTU, TCG_REG_TMP0,
|
||||
@ -905,7 +924,7 @@ static void tcg_out_goto(TCGContext *s, const tcg_insn_unit *target)
|
||||
tcg_debug_assert(ok);
|
||||
}
|
||||
|
||||
static void tcg_out_tlb_load(TCGContext *s, TCGReg addrl,
|
||||
static TCGReg tcg_out_tlb_load(TCGContext *s, TCGReg addrl,
|
||||
TCGReg addrh, MemOpIdx oi,
|
||||
tcg_insn_unit **label_ptr, bool is_load)
|
||||
{
|
||||
@ -957,6 +976,7 @@ static void tcg_out_tlb_load(TCGContext *s, TCGReg addrl,
|
||||
addrl = TCG_REG_TMP0;
|
||||
}
|
||||
tcg_out_opc_reg(s, OPC_ADD, TCG_REG_TMP0, TCG_REG_TMP2, addrl);
|
||||
return TCG_REG_TMP0;
|
||||
}
|
||||
|
||||
static void add_qemu_ldst_label(TCGContext *s, int is_ld, MemOpIdx oi,
|
||||
@ -1159,7 +1179,7 @@ static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, bool is_64)
|
||||
#else
|
||||
unsigned a_bits;
|
||||
#endif
|
||||
TCGReg base = TCG_REG_TMP0;
|
||||
TCGReg base;
|
||||
|
||||
data_regl = *args++;
|
||||
data_regh = (TCG_TARGET_REG_BITS == 32 && is_64 ? *args++ : 0);
|
||||
@ -1169,23 +1189,25 @@ static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, bool is_64)
|
||||
opc = get_memop(oi);
|
||||
|
||||
#if defined(CONFIG_SOFTMMU)
|
||||
tcg_out_tlb_load(s, addr_regl, addr_regh, oi, label_ptr, 1);
|
||||
base = tcg_out_tlb_load(s, addr_regl, addr_regh, oi, label_ptr, 1);
|
||||
tcg_out_qemu_ld_direct(s, data_regl, data_regh, base, opc, is_64);
|
||||
add_qemu_ldst_label(s, 1, oi,
|
||||
(is_64 ? TCG_TYPE_I64 : TCG_TYPE_I32),
|
||||
data_regl, data_regh, addr_regl, addr_regh,
|
||||
s->code_ptr, label_ptr);
|
||||
#else
|
||||
if (TCG_TARGET_REG_BITS > TARGET_LONG_BITS) {
|
||||
tcg_out_ext32u(s, base, addr_regl);
|
||||
addr_regl = base;
|
||||
}
|
||||
a_bits = get_alignment_bits(opc);
|
||||
if (a_bits) {
|
||||
tcg_out_test_alignment(s, true, addr_regl, a_bits);
|
||||
}
|
||||
base = addr_regl;
|
||||
if (TCG_TARGET_REG_BITS > TARGET_LONG_BITS) {
|
||||
tcg_out_ext32u(s, TCG_REG_TMP0, base);
|
||||
base = TCG_REG_TMP0;
|
||||
}
|
||||
if (guest_base != 0) {
|
||||
tcg_out_opc_reg(s, OPC_ADD, base, TCG_GUEST_BASE_REG, addr_regl);
|
||||
tcg_out_opc_reg(s, OPC_ADD, TCG_REG_TMP0, TCG_GUEST_BASE_REG, base);
|
||||
base = TCG_REG_TMP0;
|
||||
}
|
||||
tcg_out_qemu_ld_direct(s, data_regl, data_regh, base, opc, is_64);
|
||||
#endif
|
||||
@ -1231,7 +1253,7 @@ static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, bool is_64)
|
||||
#else
|
||||
unsigned a_bits;
|
||||
#endif
|
||||
TCGReg base = TCG_REG_TMP0;
|
||||
TCGReg base;
|
||||
|
||||
data_regl = *args++;
|
||||
data_regh = (TCG_TARGET_REG_BITS == 32 && is_64 ? *args++ : 0);
|
||||
@ -1241,23 +1263,25 @@ static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, bool is_64)
|
||||
opc = get_memop(oi);
|
||||
|
||||
#if defined(CONFIG_SOFTMMU)
|
||||
tcg_out_tlb_load(s, addr_regl, addr_regh, oi, label_ptr, 0);
|
||||
base = tcg_out_tlb_load(s, addr_regl, addr_regh, oi, label_ptr, 0);
|
||||
tcg_out_qemu_st_direct(s, data_regl, data_regh, base, opc);
|
||||
add_qemu_ldst_label(s, 0, oi,
|
||||
(is_64 ? TCG_TYPE_I64 : TCG_TYPE_I32),
|
||||
data_regl, data_regh, addr_regl, addr_regh,
|
||||
s->code_ptr, label_ptr);
|
||||
#else
|
||||
if (TCG_TARGET_REG_BITS > TARGET_LONG_BITS) {
|
||||
tcg_out_ext32u(s, base, addr_regl);
|
||||
addr_regl = base;
|
||||
}
|
||||
a_bits = get_alignment_bits(opc);
|
||||
if (a_bits) {
|
||||
tcg_out_test_alignment(s, false, addr_regl, a_bits);
|
||||
}
|
||||
base = addr_regl;
|
||||
if (TCG_TARGET_REG_BITS > TARGET_LONG_BITS) {
|
||||
tcg_out_ext32u(s, TCG_REG_TMP0, base);
|
||||
base = TCG_REG_TMP0;
|
||||
}
|
||||
if (guest_base != 0) {
|
||||
tcg_out_opc_reg(s, OPC_ADD, base, TCG_GUEST_BASE_REG, addr_regl);
|
||||
tcg_out_opc_reg(s, OPC_ADD, TCG_REG_TMP0, TCG_GUEST_BASE_REG, base);
|
||||
base = TCG_REG_TMP0;
|
||||
}
|
||||
tcg_out_qemu_st_direct(s, data_regl, data_regh, base, opc);
|
||||
#endif
|
||||
|
||||
@ -117,6 +117,8 @@ endif
|
||||
|
||||
%: %.c
|
||||
$(CC) $(CFLAGS) $(EXTRA_CFLAGS) $< -o $@ $(LDFLAGS)
|
||||
%: %.S
|
||||
$(CC) $(CFLAGS) $(EXTRA_CFLAGS) $< -o $@ $(LDFLAGS)
|
||||
else
|
||||
# For softmmu targets we include a different Makefile fragement as the
|
||||
# build options for bare programs are usually pretty different. They
|
||||
|
||||
@ -4,3 +4,9 @@
|
||||
VPATH += $(SRC_PATH)/tests/tcg/riscv64
|
||||
TESTS += test-div
|
||||
TESTS += noexec
|
||||
|
||||
# Disable compressed instructions for test-noc
|
||||
TESTS += test-noc
|
||||
test-noc: LDFLAGS = -nostdlib -static
|
||||
run-test-noc: QEMU_OPTS += -cpu rv64,c=false
|
||||
run-plugin-test-noc-%: QEMU_OPTS += -cpu rv64,c=false
|
||||
|
||||
32
tests/tcg/riscv64/test-noc.S
Normal file
32
tests/tcg/riscv64/test-noc.S
Normal file
@ -0,0 +1,32 @@
|
||||
#include <asm/unistd.h>
|
||||
|
||||
.text
|
||||
.globl _start
|
||||
_start:
|
||||
.option norvc
|
||||
li a0, 4 /* SIGILL */
|
||||
la a1, sa
|
||||
li a2, 0
|
||||
li a3, 8
|
||||
li a7, __NR_rt_sigaction
|
||||
scall
|
||||
|
||||
.option rvc
|
||||
li a0, 1
|
||||
j exit
|
||||
.option norvc
|
||||
|
||||
pass:
|
||||
li a0, 0
|
||||
exit:
|
||||
li a7, __NR_exit
|
||||
scall
|
||||
|
||||
.data
|
||||
/* struct kernel_sigaction sa = { .sa_handler = pass }; */
|
||||
.type sa, @object
|
||||
.size sa, 32
|
||||
sa:
|
||||
.dword pass
|
||||
.zero 24
|
||||
|
||||
Loading…
Reference in New Issue
Block a user