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microblaze/s3adsp_1800: Define macros for irq map

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Define macros for the interrupt map for the sake of self documentation.

Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
This commit is contained in:
Peter Crosthwaite 2014-02-25 16:38:19 -08:00 committed by Edgar E. Iglesias
parent aa0d1f4488
commit 05a738c4ec
1 changed files with 6 additions and 1 deletions
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7
hw/microblaze/petalogix_s3adsp1800_mmu.c
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@ -48,6 +48,10 @@
#define UARTLITE_BASEADDR 0x84000000 #define UARTLITE_BASEADDR 0x84000000
#define ETHLITE_BASEADDR 0x81000000 #define ETHLITE_BASEADDR 0x81000000
#define TIMER_IRQ 0
#define ETHLITE_IRQ 1
#define UARTLITE_IRQ 3
static void machine_cpu_reset(MicroBlazeCPU *cpu) static void machine_cpu_reset(MicroBlazeCPU *cpu)
{ {
CPUMBState *env = &cpu->env; CPUMBState *env = &cpu->env;
@ -99,7 +103,8 @@ petalogix_s3adsp1800_init(QEMUMachineInitArgs *args)
irq[i] = qdev_get_gpio_in(dev, i); irq[i] = qdev_get_gpio_in(dev, i);
} }
sysbus_create_simple("xlnx.xps-uartlite", UARTLITE_BASEADDR, irq[3]); sysbus_create_simple("xlnx.xps-uartlite", UARTLITE_BASEADDR,
irq[UARTLITE_IRQ]);
/* 2 timers at irq 2 @ 62 Mhz. */ /* 2 timers at irq 2 @ 62 Mhz. */
xilinx_timer_create(TIMER_BASEADDR, irq[0], 0, 62 * 1000000); xilinx_timer_create(TIMER_BASEADDR, irq[0], 0, 62 * 1000000);
xilinx_ethlite_create(&nd_table[0], ETHLITE_BASEADDR, irq[1], 0, 0); xilinx_ethlite_create(&nd_table[0], ETHLITE_BASEADDR, irq[1], 0, 0);