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target/mips: Do not abort on invalid instruction

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On real hardware an invalid instruction doesn't halt the world,
but usually triggers a RESERVED INSTRUCTION exception.
TCG guest code shouldn't abort QEMU anyway.

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20210617174323.2900831-2-f4bug@amsat.org>
This commit is contained in:
Philippe Mathieu-Daudé 2021-05-22 20:16:15 +02:00
parent a071578b93
commit 05d9d0359e
1 changed files with 2 additions and 2 deletions
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4
target/mips/tcg/translate.c
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@ -12151,8 +12151,8 @@ static void gen_branch(DisasContext *ctx, int insn_bytes)
tcg_gen_lookup_and_goto_ptr();
break;
default:
fprintf(stderr, "unknown branch 0x%x\n", proc_hflags);
abort();
LOG_DISAS("unknown branch 0x%x\n", proc_hflags);
gen_reserved_instruction(ctx);
}
}
}