target-arm: Implement pmccfiltr_write function
This is the function that is called when writing to the PMCCFILTR_EL0 register Signed-off-by: Alistair Francis <alistair.francis@xilinx.com> Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Message-id: 73da3da6404855b17d5ae82975a32ff3a4dcae3d.1409025949.git.peter.crosthwaite@xilinx.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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@ -650,6 +650,14 @@ void pmccntr_sync(CPUARMState *env)
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#endif
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#endif
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static void pmccfiltr_write(CPUARMState *env, const ARMCPRegInfo *ri,
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uint64_t value)
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{
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pmccntr_sync(env);
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env->cp15.pmccfiltr_el0 = value & 0x7E000000;
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pmccntr_sync(env);
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}
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static void pmcntenset_write(CPUARMState *env, const ARMCPRegInfo *ri,
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static void pmcntenset_write(CPUARMState *env, const ARMCPRegInfo *ri,
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uint64_t value)
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uint64_t value)
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{
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{
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@ -801,6 +809,7 @@ static const ARMCPRegInfo v7_cp_reginfo[] = {
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#endif
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#endif
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{ .name = "PMCCFILTR_EL0", .state = ARM_CP_STATE_AA64,
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{ .name = "PMCCFILTR_EL0", .state = ARM_CP_STATE_AA64,
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.opc0 = 3, .opc1 = 3, .crn = 14, .crm = 15, .opc2 = 7,
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.opc0 = 3, .opc1 = 3, .crn = 14, .crm = 15, .opc2 = 7,
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.writefn = pmccfiltr_write,
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.access = PL0_RW, .accessfn = pmreg_access,
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.access = PL0_RW, .accessfn = pmreg_access,
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.type = ARM_CP_IO,
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.type = ARM_CP_IO,
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.fieldoffset = offsetof(CPUARMState, cp15.pmccfiltr_el0),
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.fieldoffset = offsetof(CPUARMState, cp15.pmccfiltr_el0),
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