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ICH9: fix typo 

Signed-off-by: Cao jin <caoj.fnst@cn.fujitsu.com>
Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
This commit is contained in:
Cao jin 2016-05-17 09:41:18 +08:00 committed by Michael Tokarev
parent bbd908025c
commit 0668a06b81
2 changed files with 4 additions and 4 deletions
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4
hw/isa/lpc_ich9.c
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@ -97,8 +97,8 @@ static void ich9_cc_update(ICH9LPCState *lpc)
/*
* D30: DMI2PCI bridge
* It is arbitrarily decided how INTx lines of PCI devicesbehind the bridge
* are connected to pirq lines. Our choice is PIRQ[E-H].
* It is arbitrarily decided how INTx lines of PCI devices behind
* the bridge are connected to pirq lines. Our choice is PIRQ[E-H].
* INT[A-D] are connected to PIRQ[E-H]
*/
for (pci_intx = 0; pci_intx < PCI_NUM_PINS; pci_intx++) {

4
include/hw/i386/ich9.h
View File

@ -35,7 +35,7 @@ typedef struct ICH9LPCState {
/* (pci device, intx) -> pirq
* In real chipset case, the unused slots are never used
* as ICH9 supports only D25-D32 irq routing.
* as ICH9 supports only D25-D31 irq routing.
* On the other hand in qemu case, any slot/function can be populated
* via command line option.
* So fallback interrupt routing for any devices in any slots is necessary.
@ -181,7 +181,7 @@ Object *ich9_lpc_find(void);
#define ICH9_SATA1_DEV 31
#define ICH9_SATA1_FUNC 2
/* D30:F1 power management I/O registers
/* D31:F0 power management I/O registers
offset from the address ICH9_LPC_PMBASE */
/* ICH9 LPC PM I/O registers are 128 ports and 128-aligned */