target-arm: Break out mpidr_read_val()
Break out mpidr_read_val() to allow future sharing of the code that conditionally sets the M and U bits of MPIDR. No functional changes. Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Message-id: 1442135278-25281-8-git-send-email-edgar.iglesias@gmail.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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@ -2457,7 +2457,7 @@ static uint64_t midr_read(CPUARMState *env, const ARMCPRegInfo *ri)
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return raw_read(env, ri);
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return raw_read(env, ri);
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}
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}
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static uint64_t mpidr_read(CPUARMState *env, const ARMCPRegInfo *ri)
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static uint64_t mpidr_read_val(CPUARMState *env)
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{
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{
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ARMCPU *cpu = ARM_CPU(arm_env_get_cpu(env));
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ARMCPU *cpu = ARM_CPU(arm_env_get_cpu(env));
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uint64_t mpidr = cpu->mp_affinity;
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uint64_t mpidr = cpu->mp_affinity;
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@ -2475,6 +2475,11 @@ static uint64_t mpidr_read(CPUARMState *env, const ARMCPRegInfo *ri)
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return mpidr;
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return mpidr;
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}
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}
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static uint64_t mpidr_read(CPUARMState *env, const ARMCPRegInfo *ri)
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{
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return mpidr_read_val(env);
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}
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static const ARMCPRegInfo mpidr_cp_reginfo[] = {
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static const ARMCPRegInfo mpidr_cp_reginfo[] = {
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{ .name = "MPIDR", .state = ARM_CP_STATE_BOTH,
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{ .name = "MPIDR", .state = ARM_CP_STATE_BOTH,
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.opc0 = 3, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 5,
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.opc0 = 3, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 5,
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