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target/openrisc: Prefer fast cpu_env() over slower CPU QOM cast macro

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Mechanical patch produced running the command documented
in scripts/coccinelle/cpu_env.cocci_template header.

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-ID: <20240129164514.73104-21-philmd@linaro.org>
Signed-off-by: Thomas Huth <thuth@redhat.com>
This commit is contained in:
Philippe Mathieu-Daudé 2024-01-29 17:45:02 +01:00 committed by Thomas Huth
parent 6fed7e43fa
commit 074bd799e7
3 changed files with 6 additions and 12 deletions
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6
target/openrisc/gdbstub.c
View File

@ -23,8 +23,7 @@
int openrisc_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n) int openrisc_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n)
{ {
OpenRISCCPU *cpu = OPENRISC_CPU(cs); CPUOpenRISCState *env = cpu_env(cs);
CPUOpenRISCState *env = &cpu->env;
if (n < 32) { if (n < 32) {
return gdb_get_reg32(mem_buf, cpu_get_gpr(env, n)); return gdb_get_reg32(mem_buf, cpu_get_gpr(env, n));
@ -48,9 +47,8 @@ int openrisc_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n)
int openrisc_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n) int openrisc_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n)
{ {
OpenRISCCPU *cpu = OPENRISC_CPU(cs);
CPUClass *cc = CPU_GET_CLASS(cs); CPUClass *cc = CPU_GET_CLASS(cs);
CPUOpenRISCState *env = &cpu->env; CPUOpenRISCState *env = cpu_env(cs);
uint32_t tmp; uint32_t tmp;
if (n > cc->gdb_num_core_regs) { if (n > cc->gdb_num_core_regs) {

6
target/openrisc/interrupt.c
View File

@ -29,8 +29,7 @@
void openrisc_cpu_do_interrupt(CPUState *cs) void openrisc_cpu_do_interrupt(CPUState *cs)
{ {
OpenRISCCPU *cpu = OPENRISC_CPU(cs); CPUOpenRISCState *env = cpu_env(cs);
CPUOpenRISCState *env = &cpu->env;
int exception = cs->exception_index; int exception = cs->exception_index;
env->epcr = env->pc; env->epcr = env->pc;
@ -105,8 +104,7 @@ void openrisc_cpu_do_interrupt(CPUState *cs)
bool openrisc_cpu_exec_interrupt(CPUState *cs, int interrupt_request) bool openrisc_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
{ {
OpenRISCCPU *cpu = OPENRISC_CPU(cs); CPUOpenRISCState *env = cpu_env(cs);
CPUOpenRISCState *env = &cpu->env;
int idx = -1; int idx = -1;
if ((interrupt_request & CPU_INTERRUPT_HARD) && (env->sr & SR_IEE)) { if ((interrupt_request & CPU_INTERRUPT_HARD) && (env->sr & SR_IEE)) {

6
target/openrisc/translate.c
View File

@ -1564,8 +1564,7 @@ static void openrisc_tr_insn_start(DisasContextBase *dcbase, CPUState *cs)
static void openrisc_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs) static void openrisc_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs)
{ {
DisasContext *dc = container_of(dcbase, DisasContext, base); DisasContext *dc = container_of(dcbase, DisasContext, base);
OpenRISCCPU *cpu = OPENRISC_CPU(cs); uint32_t insn = translator_ldl(cpu_env(cs), &dc->base, dc->base.pc_next);
uint32_t insn = translator_ldl(&cpu->env, &dc->base, dc->base.pc_next);
if (!decode(dc, insn)) { if (!decode(dc, insn)) {
gen_illegal_exception(dc); gen_illegal_exception(dc);
@ -1668,8 +1667,7 @@ void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int *max_insns,
void openrisc_cpu_dump_state(CPUState *cs, FILE *f, int flags) void openrisc_cpu_dump_state(CPUState *cs, FILE *f, int flags)
{ {
OpenRISCCPU *cpu = OPENRISC_CPU(cs); CPUOpenRISCState *env = cpu_env(cs);
CPUOpenRISCState *env = &cpu->env;
int i; int i;
qemu_fprintf(f, "PC=%08x\n", env->pc); qemu_fprintf(f, "PC=%08x\n", env->pc);