hw/char/pl011: Replace magic values by register field definitions
0x400 is Data Register Break Error (DR_BE), 0x10 is Line Control Register Fifo Enabled (LCR_FEN) and 0x1 is Send Break (LCR_BRK). Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20230522153144.30610-7-philmd@linaro.org>
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@ -54,6 +54,9 @@ DeviceState *pl011_create(hwaddr addr, qemu_irq irq, Chardev *chr)
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#define PL011_FLAG_TXFF 0x20
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#define PL011_FLAG_RXFE 0x10
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/* Data Register, UARTDR */
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#define DR_BE (1 << 10)
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/* Interrupt status bits in UARTRIS, UARTMIS, UARTIMSC */
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#define INT_OE (1 << 10)
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#define INT_BE (1 << 9)
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@ -69,6 +72,10 @@ DeviceState *pl011_create(hwaddr addr, qemu_irq irq, Chardev *chr)
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#define INT_E (INT_OE | INT_BE | INT_PE | INT_FE)
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#define INT_MS (INT_RI | INT_DSR | INT_DCD | INT_CTS)
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/* Line Control Register, UARTLCR_H */
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#define LCR_FEN (1 << 4)
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#define LCR_BRK (1 << 0)
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static const unsigned char pl011_id_arm[8] =
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{ 0x11, 0x10, 0x14, 0x00, 0x0d, 0xf0, 0x05, 0xb1 };
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static const unsigned char pl011_id_luminary[8] =
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@ -116,7 +123,7 @@ static void pl011_update(PL011State *s)
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static bool pl011_is_fifo_enabled(PL011State *s)
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{
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return (s->lcr & 0x10) != 0;
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return (s->lcr & LCR_FEN) != 0;
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}
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static inline unsigned pl011_get_fifo_depth(PL011State *s)
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@ -218,7 +225,7 @@ static void pl011_set_read_trigger(PL011State *s)
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the threshold. However linux only reads the FIFO in response to an
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interrupt. Triggering the interrupt when the FIFO is non-empty seems
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to make things work. */
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if (s->lcr & 0x10)
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if (s->lcr & LCR_FEN)
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s->read_trigger = (s->ifl >> 1) & 0x1c;
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else
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#endif
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@ -281,11 +288,11 @@ static void pl011_write(void *opaque, hwaddr offset,
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break;
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case 11: /* UARTLCR_H */
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/* Reset the FIFO state on FIFO enable or disable */
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if ((s->lcr ^ value) & 0x10) {
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if ((s->lcr ^ value) & LCR_FEN) {
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pl011_reset_fifo(s);
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}
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if ((s->lcr ^ value) & 0x1) {
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int break_enable = value & 0x1;
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if ((s->lcr ^ value) & LCR_BRK) {
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int break_enable = value & LCR_BRK;
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qemu_chr_fe_ioctl(&s->chr, CHR_IOCTL_SERIAL_SET_BREAK,
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&break_enable);
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}
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@ -359,8 +366,9 @@ static void pl011_receive(void *opaque, const uint8_t *buf, int size)
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static void pl011_event(void *opaque, QEMUChrEvent event)
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{
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if (event == CHR_EVENT_BREAK)
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pl011_put_fifo(opaque, 0x400);
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if (event == CHR_EVENT_BREAK) {
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pl011_put_fifo(opaque, DR_BE);
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}
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}
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static void pl011_clock_update(void *opaque, ClockEvent event)
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