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target/riscv: Implement address masking functions required for RISC-V Pointer Masking extension 

Signed-off-by: Anatoly Parshintsev <kupokupokupopo@gmail.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20211025173609.2724490-8-space.monkey.delivers@gmail.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
This commit is contained in:
Anatoly Parshintsev 2021-10-25 20:36:08 +03:00 committed by Alistair Francis
parent c655df7fe0
commit 0774a7a1ff
3 changed files with 57 additions and 2 deletions
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2
target/riscv/cpu.h
View File

@ -410,6 +410,8 @@ FIELD(TB_FLAGS, HLSX, 10, 1)
FIELD(TB_FLAGS, MSTATUS_HS_FS, 11, 2)
/* The combination of MXL/SXL/UXL that applies to the current cpu mode. */
FIELD(TB_FLAGS, XL, 13, 2)
/* If PointerMasking should be applied */
FIELD(TB_FLAGS, PM_ENABLED, 15, 1)
#ifdef TARGET_RISCV32
#define riscv_cpu_mxl(env) ((void)(env), MXL_RV32)

18
target/riscv/cpu_helper.c
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@ -107,6 +107,24 @@ void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulong *pc,
flags = FIELD_DP32(flags, TB_FLAGS, MSTATUS_HS_FS,
get_field(env->mstatus_hs, MSTATUS_FS));
}
if (riscv_has_ext(env, RVJ)) {
int priv = flags & TB_FLAGS_PRIV_MMU_MASK;
bool pm_enabled = false;
switch (priv) {
case PRV_U:
pm_enabled = env->mmte & U_PM_ENABLE;
break;
case PRV_S:
pm_enabled = env->mmte & S_PM_ENABLE;
break;
case PRV_M:
pm_enabled = env->mmte & M_PM_ENABLE;
break;
default:
g_assert_not_reached();
}
flags = FIELD_DP32(flags, TB_FLAGS, PM_ENABLED, pm_enabled);
}
#endif
flags = FIELD_DP32(flags, TB_FLAGS, XL, cpu_get_xl(env));

39
target/riscv/translate.c
View File

@ -36,6 +36,9 @@ static TCGv cpu_gpr[32], cpu_pc, cpu_vl;
static TCGv_i64 cpu_fpr[32]; /* assume F and D extensions */
static TCGv load_res;
static TCGv load_val;
/* globals for PM CSRs */
static TCGv pm_mask[4];
static TCGv pm_base[4];
#include "exec/gen-icount.h"
@ -83,6 +86,10 @@ typedef struct DisasContext {
TCGv zero;
/* Space for 3 operands plus 1 extra for address computation. */
TCGv temp[4];
/* PointerMasking extension */
bool pm_enabled;
TCGv pm_mask;
TCGv pm_base;
} DisasContext;
static inline bool has_ext(DisasContext *ctx, uint32_t ext)
@ -272,11 +279,20 @@ static void gen_jal(DisasContext *ctx, int rd, target_ulong imm)
}
/*
* Temp stub: generates address adjustment for PointerMasking
* Generates address adjustment for PointerMasking
*/
static TCGv gen_pm_adjust_address(DisasContext *s, TCGv src)
{
return src;
TCGv temp;
if (!s->pm_enabled) {
/* Load unmodified address */
return src;
} else {
temp = temp_new(s);
tcg_gen_andc_tl(temp, src, s->pm_mask);
tcg_gen_or_tl(temp, temp, s->pm_base);
return temp;
}
}
#ifndef CONFIG_USER_ONLY
@ -622,6 +638,10 @@ static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
ctx->cs = cs;
ctx->ntemp = 0;
memset(ctx->temp, 0, sizeof(ctx->temp));
ctx->pm_enabled = FIELD_EX32(tb_flags, TB_FLAGS, PM_ENABLED);
int priv = tb_flags & TB_FLAGS_PRIV_MMU_MASK;
ctx->pm_mask = pm_mask[priv];
ctx->pm_base = pm_base[priv];
ctx->zero = tcg_constant_tl(0);
}
@ -735,4 +755,19 @@ void riscv_translate_init(void)
"load_res");
load_val = tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, load_val),
"load_val");
#ifndef CONFIG_USER_ONLY
/* Assign PM CSRs to tcg globals */
pm_mask[PRV_U] =
tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, upmmask), "upmmask");
pm_base[PRV_U] =
tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, upmbase), "upmbase");
pm_mask[PRV_S] =
tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, spmmask), "spmmask");
pm_base[PRV_S] =
tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, spmbase), "spmbase");
pm_mask[PRV_M] =
tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, mpmmask), "mpmmask");
pm_base[PRV_M] =
tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, mpmbase), "mpmbase");
#endif
}