target-i386/helper: remove ESP macro
Signed-off-by: liguang <lig.fnst@cn.fujitsu.com> Reviewed-by: Andreas Färber <afaerber@suse.de> Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
This commit is contained in:
liguang
Blue Swirl
parent
c12dddd791
commit
08b3ded6bd
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@ -1101,8 +1101,6 @@ static inline int cpu_mmu_index (CPUX86State *env)
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? MMU_KSMAP_IDX : MMU_KERNEL_IDX;
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}
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#undef ESP
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#define ESP (env->regs[R_ESP])
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#undef ESI
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#define ESI (env->regs[R_ESI])
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#undef EDI
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@ -328,7 +328,7 @@ static void switch_tss(CPUX86State *env, int tss_selector,
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cpu_stl_kernel(env, env->tr.base + (0x28 + 1 * 4), env->regs[R_ECX]);
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cpu_stl_kernel(env, env->tr.base + (0x28 + 2 * 4), env->regs[R_EDX]);
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cpu_stl_kernel(env, env->tr.base + (0x28 + 3 * 4), env->regs[R_EBX]);
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cpu_stl_kernel(env, env->tr.base + (0x28 + 4 * 4), ESP);
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cpu_stl_kernel(env, env->tr.base + (0x28 + 4 * 4), env->regs[R_ESP]);
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cpu_stl_kernel(env, env->tr.base + (0x28 + 5 * 4), env->regs[R_EBP]);
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cpu_stl_kernel(env, env->tr.base + (0x28 + 6 * 4), ESI);
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cpu_stl_kernel(env, env->tr.base + (0x28 + 7 * 4), EDI);
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@ -344,7 +344,7 @@ static void switch_tss(CPUX86State *env, int tss_selector,
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cpu_stw_kernel(env, env->tr.base + (0x12 + 1 * 2), env->regs[R_ECX]);
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cpu_stw_kernel(env, env->tr.base + (0x12 + 2 * 2), env->regs[R_EDX]);
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cpu_stw_kernel(env, env->tr.base + (0x12 + 3 * 2), env->regs[R_EBX]);
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cpu_stw_kernel(env, env->tr.base + (0x12 + 4 * 2), ESP);
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cpu_stw_kernel(env, env->tr.base + (0x12 + 4 * 2), env->regs[R_ESP]);
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cpu_stw_kernel(env, env->tr.base + (0x12 + 5 * 2), env->regs[R_EBP]);
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cpu_stw_kernel(env, env->tr.base + (0x12 + 6 * 2), ESI);
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cpu_stw_kernel(env, env->tr.base + (0x12 + 7 * 2), EDI);
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@ -400,7 +400,7 @@ static void switch_tss(CPUX86State *env, int tss_selector,
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env->regs[R_ECX] = new_regs[1];
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env->regs[R_EDX] = new_regs[2];
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env->regs[R_EBX] = new_regs[3];
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ESP = new_regs[4];
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env->regs[R_ESP] = new_regs[4];
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env->regs[R_EBP] = new_regs[5];
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ESI = new_regs[6];
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EDI = new_regs[7];
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@ -502,20 +502,22 @@ static int exception_has_error_code(int intno)
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}
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#ifdef TARGET_X86_64
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#define SET_ESP(val, sp_mask) \
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do { \
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if ((sp_mask) == 0xffff) { \
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ESP = (ESP & ~0xffff) | ((val) & 0xffff); \
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} else if ((sp_mask) == 0xffffffffLL) { \
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ESP = (uint32_t)(val); \
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} else { \
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ESP = (val); \
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} \
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#define SET_ESP(val, sp_mask) \
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do { \
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if ((sp_mask) == 0xffff) { \
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env->regs[R_ESP] = (env->regs[R_ESP] & ~0xffff) | \
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((val) & 0xffff); \
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} else if ((sp_mask) == 0xffffffffLL) { \
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env->regs[R_ESP] = (uint32_t)(val); \
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} else { \
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env->regs[R_ESP] = (val); \
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} \
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} while (0)
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#else
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#define SET_ESP(val, sp_mask) \
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do { \
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ESP = (ESP & ~(sp_mask)) | ((val) & (sp_mask)); \
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#define SET_ESP(val, sp_mask) \
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do { \
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env->regs[R_ESP] = (env->regs[R_ESP] & ~(sp_mask)) | \
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((val) & (sp_mask)); \
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} while (0)
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#endif
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@ -598,7 +600,7 @@ static void do_interrupt_protected(CPUX86State *env, int intno, int is_int,
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} else {
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mask = 0xffff;
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}
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esp = (ESP - (2 << shift)) & mask;
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esp = (env->regs[R_ESP] - (2 << shift)) & mask;
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ssp = env->segs[R_SS].base + esp;
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if (shift) {
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cpu_stl_kernel(env, ssp, error_code);
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@ -680,7 +682,7 @@ static void do_interrupt_protected(CPUX86State *env, int intno, int is_int,
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new_stack = 0;
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sp_mask = get_sp_mask(env->segs[R_SS].flags);
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ssp = env->segs[R_SS].base;
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esp = ESP;
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esp = env->regs[R_ESP];
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dpl = cpl;
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} else {
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raise_exception_err(env, EXCP0D_GPF, selector & 0xfffc);
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@ -709,7 +711,7 @@ static void do_interrupt_protected(CPUX86State *env, int intno, int is_int,
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PUSHL(ssp, esp, sp_mask, env->segs[R_ES].selector);
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}
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PUSHL(ssp, esp, sp_mask, env->segs[R_SS].selector);
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PUSHL(ssp, esp, sp_mask, ESP);
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PUSHL(ssp, esp, sp_mask, env->regs[R_ESP]);
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}
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PUSHL(ssp, esp, sp_mask, cpu_compute_eflags(env));
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PUSHL(ssp, esp, sp_mask, env->segs[R_CS].selector);
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@ -726,7 +728,7 @@ static void do_interrupt_protected(CPUX86State *env, int intno, int is_int,
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PUSHW(ssp, esp, sp_mask, env->segs[R_ES].selector);
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}
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PUSHW(ssp, esp, sp_mask, env->segs[R_SS].selector);
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PUSHW(ssp, esp, sp_mask, ESP);
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PUSHW(ssp, esp, sp_mask, env->regs[R_ESP]);
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}
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PUSHW(ssp, esp, sp_mask, cpu_compute_eflags(env));
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PUSHW(ssp, esp, sp_mask, env->segs[R_CS].selector);
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@ -888,7 +890,7 @@ static void do_interrupt64(CPUX86State *env, int intno, int is_int,
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if (ist != 0) {
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esp = get_rsp_from_tss(env, ist + 3);
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} else {
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esp = ESP;
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esp = env->regs[R_ESP];
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}
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esp &= ~0xfLL; /* align stack */
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dpl = cpl;
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@ -899,7 +901,7 @@ static void do_interrupt64(CPUX86State *env, int intno, int is_int,
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}
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PUSHQ(esp, env->segs[R_SS].selector);
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PUSHQ(esp, ESP);
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PUSHQ(esp, env->regs[R_ESP]);
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PUSHQ(esp, cpu_compute_eflags(env));
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PUSHQ(esp, env->segs[R_CS].selector);
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PUSHQ(esp, old_eip);
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@ -911,7 +913,7 @@ static void do_interrupt64(CPUX86State *env, int intno, int is_int,
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ss = 0 | dpl;
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cpu_x86_load_seg_cache(env, R_SS, ss, 0, 0, 0);
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}
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ESP = esp;
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env->regs[R_ESP] = esp;
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selector = (selector & ~3) | dpl;
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cpu_x86_load_seg_cache(env, R_CS, selector,
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@ -1069,7 +1071,7 @@ static void do_interrupt_real(CPUX86State *env, int intno, int is_int,
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ptr = dt->base + intno * 4;
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offset = cpu_lduw_kernel(env, ptr);
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selector = cpu_lduw_kernel(env, ptr + 2);
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esp = ESP;
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esp = env->regs[R_ESP];
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ssp = env->segs[R_SS].base;
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if (is_int) {
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old_eip = next_eip;
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@ -1083,7 +1085,7 @@ static void do_interrupt_real(CPUX86State *env, int intno, int is_int,
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PUSHW(ssp, esp, 0xffff, old_eip);
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/* update processor state */
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ESP = (ESP & ~0xffff) | (esp & 0xffff);
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env->regs[R_ESP] = (env->regs[R_ESP] & ~0xffff) | (esp & 0xffff);
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env->eip = offset;
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env->segs[R_CS].selector = selector;
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env->segs[R_CS].base = (selector << 4);
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@ -1171,7 +1173,7 @@ static void do_interrupt_all(CPUX86State *env, int intno, int is_int,
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env->hflags & HF_CPL_MASK,
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env->segs[R_CS].selector, EIP,
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(int)env->segs[R_CS].base + EIP,
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env->segs[R_SS].selector, ESP);
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env->segs[R_SS].selector, env->regs[R_ESP]);
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if (intno == 0x0e) {
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qemu_log(" CR2=" TARGET_FMT_lx, env->cr[2]);
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} else {
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@ -1273,7 +1275,7 @@ void helper_enter_level(CPUX86State *env, int level, int data32,
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esp_mask = get_sp_mask(env->segs[R_SS].flags);
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ssp = env->segs[R_SS].base;
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ebp = env->regs[R_EBP];
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esp = ESP;
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esp = env->regs[R_ESP];
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if (data32) {
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/* 32 bit */
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esp -= 4;
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@ -1306,7 +1308,7 @@ void helper_enter64_level(CPUX86State *env, int level, int data64,
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target_ulong esp, ebp;
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ebp = env->regs[R_EBP];
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esp = ESP;
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esp = env->regs[R_ESP];
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if (data64) {
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/* 64 bit */
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@ -1653,7 +1655,7 @@ void helper_lcall_real(CPUX86State *env, int new_cs, target_ulong new_eip1,
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target_ulong ssp;
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new_eip = new_eip1;
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esp = ESP;
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esp = env->regs[R_ESP];
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esp_mask = get_sp_mask(env->segs[R_SS].flags);
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ssp = env->segs[R_SS].base;
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if (shift) {
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@ -1721,11 +1723,11 @@ void helper_lcall_protected(CPUX86State *env, int new_cs, target_ulong new_eip,
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target_ulong rsp;
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/* 64 bit case */
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rsp = ESP;
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rsp = env->regs[R_ESP];
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PUSHQ(rsp, env->segs[R_CS].selector);
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PUSHQ(rsp, next_eip);
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/* from this point, not restartable */
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ESP = rsp;
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env->regs[R_ESP] = rsp;
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cpu_x86_load_seg_cache(env, R_CS, (new_cs & 0xfffc) | cpl,
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get_seg_base(e1, e2),
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get_seg_limit(e1, e2), e2);
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@ -1733,7 +1735,7 @@ void helper_lcall_protected(CPUX86State *env, int new_cs, target_ulong new_eip,
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} else
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#endif
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{
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sp = ESP;
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sp = env->regs[R_ESP];
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sp_mask = get_sp_mask(env->segs[R_SS].flags);
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ssp = env->segs[R_SS].base;
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if (shift) {
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@ -1809,9 +1811,9 @@ void helper_lcall_protected(CPUX86State *env, int new_cs, target_ulong new_eip,
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if (!(e2 & DESC_C_MASK) && dpl < cpl) {
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/* to inner privilege */
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get_ss_esp_from_tss(env, &ss, &sp, dpl);
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LOG_PCALL("new ss:esp=%04x:%08x param_count=%d ESP=" TARGET_FMT_lx
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LOG_PCALL("new ss:esp=%04x:%08x param_count=%d env->regs[R_ESP]=" TARGET_FMT_lx
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"\n",
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ss, sp, param_count, ESP);
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ss, sp, param_count, env->regs[R_ESP]);
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if ((ss & 0xfffc) == 0) {
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raise_exception_err(env, EXCP0A_TSS, ss & 0xfffc);
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}
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@ -1843,17 +1845,17 @@ void helper_lcall_protected(CPUX86State *env, int new_cs, target_ulong new_eip,
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ssp = get_seg_base(ss_e1, ss_e2);
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if (shift) {
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PUSHL(ssp, sp, sp_mask, env->segs[R_SS].selector);
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PUSHL(ssp, sp, sp_mask, ESP);
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PUSHL(ssp, sp, sp_mask, env->regs[R_ESP]);
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for (i = param_count - 1; i >= 0; i--) {
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val = cpu_ldl_kernel(env, old_ssp + ((ESP + i * 4) &
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val = cpu_ldl_kernel(env, old_ssp + ((env->regs[R_ESP] + i * 4) &
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old_sp_mask));
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PUSHL(ssp, sp, sp_mask, val);
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}
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} else {
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PUSHW(ssp, sp, sp_mask, env->segs[R_SS].selector);
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PUSHW(ssp, sp, sp_mask, ESP);
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PUSHW(ssp, sp, sp_mask, env->regs[R_ESP]);
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for (i = param_count - 1; i >= 0; i--) {
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val = cpu_lduw_kernel(env, old_ssp + ((ESP + i * 2) &
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val = cpu_lduw_kernel(env, old_ssp + ((env->regs[R_ESP] + i * 2) &
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old_sp_mask));
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PUSHW(ssp, sp, sp_mask, val);
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}
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@ -1861,7 +1863,7 @@ void helper_lcall_protected(CPUX86State *env, int new_cs, target_ulong new_eip,
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new_stack = 1;
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} else {
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/* to same privilege */
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sp = ESP;
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sp = env->regs[R_ESP];
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sp_mask = get_sp_mask(env->segs[R_SS].flags);
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ssp = env->segs[R_SS].base;
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/* push_size = (4 << shift); */
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@ -1905,7 +1907,7 @@ void helper_iret_real(CPUX86State *env, int shift)
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int eflags_mask;
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sp_mask = 0xffff; /* XXXX: use SS segment size? */
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sp = ESP;
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sp = env->regs[R_ESP];
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ssp = env->segs[R_SS].base;
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if (shift == 1) {
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/* 32 bits */
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@ -1919,7 +1921,7 @@ void helper_iret_real(CPUX86State *env, int shift)
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POPW(ssp, sp, sp_mask, new_cs);
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POPW(ssp, sp, sp_mask, new_eflags);
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}
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ESP = (ESP & ~sp_mask) | (sp & sp_mask);
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env->regs[R_ESP] = (env->regs[R_ESP] & ~sp_mask) | (sp & sp_mask);
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env->segs[R_CS].selector = new_cs;
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env->segs[R_CS].base = (new_cs << 4);
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env->eip = new_eip;
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@ -1978,7 +1980,7 @@ static inline void helper_ret_protected(CPUX86State *env, int shift,
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{
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sp_mask = get_sp_mask(env->segs[R_SS].flags);
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}
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sp = ESP;
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sp = env->regs[R_ESP];
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ssp = env->segs[R_SS].base;
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new_eflags = 0; /* avoid warning */
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#ifdef TARGET_X86_64
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@ -2179,7 +2181,7 @@ static inline void helper_ret_protected(CPUX86State *env, int shift,
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load_seg_vm(env, R_GS, new_gs & 0xffff);
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env->eip = new_eip & 0xffff;
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ESP = new_esp;
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env->regs[R_ESP] = new_esp;
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}
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void helper_iret_protected(CPUX86State *env, int shift, int next_eip)
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@ -2248,7 +2250,7 @@ void helper_sysenter(CPUX86State *env)
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DESC_G_MASK | DESC_B_MASK | DESC_P_MASK |
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DESC_S_MASK |
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DESC_W_MASK | DESC_A_MASK);
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ESP = env->sysenter_esp;
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env->regs[R_ESP] = env->sysenter_esp;
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EIP = env->sysenter_eip;
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}
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@ -2288,7 +2290,7 @@ void helper_sysexit(CPUX86State *env, int dflag)
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DESC_S_MASK | (3 << DESC_DPL_SHIFT) |
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DESC_W_MASK | DESC_A_MASK);
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}
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ESP = env->regs[R_ECX];
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env->regs[R_ESP] = env->regs[R_ECX];
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EIP = env->regs[R_EDX];
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}
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@ -86,7 +86,7 @@ void do_smm_enter(CPUX86State *env)
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stq_phys(sm_state + 0x7ff0, env->regs[R_ECX]);
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stq_phys(sm_state + 0x7fe8, env->regs[R_EDX]);
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stq_phys(sm_state + 0x7fe0, env->regs[R_EBX]);
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stq_phys(sm_state + 0x7fd8, ESP);
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stq_phys(sm_state + 0x7fd8, env->regs[R_ESP]);
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stq_phys(sm_state + 0x7fd0, env->regs[R_EBP]);
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stq_phys(sm_state + 0x7fc8, ESI);
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stq_phys(sm_state + 0x7fc0, EDI);
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@ -112,7 +112,7 @@ void do_smm_enter(CPUX86State *env)
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stl_phys(sm_state + 0x7fec, EDI);
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stl_phys(sm_state + 0x7fe8, ESI);
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stl_phys(sm_state + 0x7fe4, env->regs[R_EBP]);
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stl_phys(sm_state + 0x7fe0, ESP);
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stl_phys(sm_state + 0x7fe0, env->regs[R_ESP]);
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stl_phys(sm_state + 0x7fdc, env->regs[R_EBX]);
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stl_phys(sm_state + 0x7fd8, env->regs[R_EDX]);
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stl_phys(sm_state + 0x7fd4, env->regs[R_ECX]);
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@ -217,7 +217,7 @@ void helper_rsm(CPUX86State *env)
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env->regs[R_ECX] = ldq_phys(sm_state + 0x7ff0);
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env->regs[R_EDX] = ldq_phys(sm_state + 0x7fe8);
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env->regs[R_EBX] = ldq_phys(sm_state + 0x7fe0);
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ESP = ldq_phys(sm_state + 0x7fd8);
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env->regs[R_ESP] = ldq_phys(sm_state + 0x7fd8);
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||||
env->regs[R_EBP] = ldq_phys(sm_state + 0x7fd0);
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||||
ESI = ldq_phys(sm_state + 0x7fc8);
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||||
EDI = ldq_phys(sm_state + 0x7fc0);
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||||
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@ -247,7 +247,7 @@ void helper_rsm(CPUX86State *env)
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|||
EDI = ldl_phys(sm_state + 0x7fec);
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||||
ESI = ldl_phys(sm_state + 0x7fe8);
|
||||
env->regs[R_EBP] = ldl_phys(sm_state + 0x7fe4);
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||||
ESP = ldl_phys(sm_state + 0x7fe0);
|
||||
env->regs[R_ESP] = ldl_phys(sm_state + 0x7fe0);
|
||||
env->regs[R_EBX] = ldl_phys(sm_state + 0x7fdc);
|
||||
env->regs[R_EDX] = ldl_phys(sm_state + 0x7fd8);
|
||||
env->regs[R_ECX] = ldl_phys(sm_state + 0x7fd4);
|
||||
|
|
|
|||
|
|
@ -171,7 +171,7 @@ void helper_vmrun(CPUX86State *env, int aflag, int next_eip_addend)
|
|||
|
||||
stq_phys(env->vm_hsave + offsetof(struct vmcb, save.rip),
|
||||
EIP + next_eip_addend);
|
||||
stq_phys(env->vm_hsave + offsetof(struct vmcb, save.rsp), ESP);
|
||||
stq_phys(env->vm_hsave + offsetof(struct vmcb, save.rsp), env->regs[R_ESP]);
|
||||
stq_phys(env->vm_hsave + offsetof(struct vmcb, save.rax), env->regs[R_EAX]);
|
||||
|
||||
/* load the interception bitmaps so we do not need to access the
|
||||
|
|
@ -250,7 +250,7 @@ void helper_vmrun(CPUX86State *env, int aflag, int next_eip_addend)
|
|||
|
||||
EIP = ldq_phys(env->vm_vmcb + offsetof(struct vmcb, save.rip));
|
||||
env->eip = EIP;
|
||||
ESP = ldq_phys(env->vm_vmcb + offsetof(struct vmcb, save.rsp));
|
||||
env->regs[R_ESP] = ldq_phys(env->vm_vmcb + offsetof(struct vmcb, save.rsp));
|
||||
env->regs[R_EAX] = ldq_phys(env->vm_vmcb + offsetof(struct vmcb, save.rax));
|
||||
env->dr[7] = ldq_phys(env->vm_vmcb + offsetof(struct vmcb, save.dr7));
|
||||
env->dr[6] = ldq_phys(env->vm_vmcb + offsetof(struct vmcb, save.dr6));
|
||||
|
|
@ -606,7 +606,7 @@ void helper_vmexit(CPUX86State *env, uint32_t exit_code, uint64_t exit_info_1)
|
|||
cpu_compute_eflags(env));
|
||||
stq_phys(env->vm_vmcb + offsetof(struct vmcb, save.rip),
|
||||
env->eip);
|
||||
stq_phys(env->vm_vmcb + offsetof(struct vmcb, save.rsp), ESP);
|
||||
stq_phys(env->vm_vmcb + offsetof(struct vmcb, save.rsp), env->regs[R_ESP]);
|
||||
stq_phys(env->vm_vmcb + offsetof(struct vmcb, save.rax), env->regs[R_EAX]);
|
||||
stq_phys(env->vm_vmcb + offsetof(struct vmcb, save.dr7), env->dr[7]);
|
||||
stq_phys(env->vm_vmcb + offsetof(struct vmcb, save.dr6), env->dr[6]);
|
||||
|
|
@ -658,7 +658,7 @@ void helper_vmexit(CPUX86State *env, uint32_t exit_code, uint64_t exit_info_1)
|
|||
R_DS);
|
||||
|
||||
EIP = ldq_phys(env->vm_hsave + offsetof(struct vmcb, save.rip));
|
||||
ESP = ldq_phys(env->vm_hsave + offsetof(struct vmcb, save.rsp));
|
||||
env->regs[R_ESP] = ldq_phys(env->vm_hsave + offsetof(struct vmcb, save.rsp));
|
||||
env->regs[R_EAX] = ldq_phys(env->vm_hsave + offsetof(struct vmcb, save.rax));
|
||||
|
||||
env->dr[6] = ldq_phys(env->vm_hsave + offsetof(struct vmcb, save.dr6));
|
||||
|
|
|
|||
Loading…
Reference in New Issue