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target/ppc: implement vclrlb 

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
Message-Id: <20220225210936.1749575-16-matheus.ferst@eldorado.org.br>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
This commit is contained in:
Matheus Ferst 2022-03-02 06:51:37 +01:00 committed by Cédric Le Goater
parent fb5303cc05
commit 08d512e1b9
2 changed files with 42 additions and 0 deletions
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2
target/ppc/insn32.decode
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@ -529,6 +529,8 @@ VSTRIBR 000100 ..... 00001 ..... . 0000001101 @VX_tb_rc
VSTRIHL 000100 ..... 00010 ..... . 0000001101 @VX_tb_rc
VSTRIHR 000100 ..... 00011 ..... . 0000001101 @VX_tb_rc
VCLRLB 000100 ..... ..... ..... 00110001101 @VX
# VSX Load/Store Instructions
LXV 111101 ..... ..... ............ . 001 @DQ_TSX

40
target/ppc/translate/vmx-impl.c.inc
View File

@ -1940,6 +1940,46 @@ TRANS(VSTRIBR, do_vstri, gen_helper_VSTRIBR)
TRANS(VSTRIHL, do_vstri, gen_helper_VSTRIHL)
TRANS(VSTRIHR, do_vstri, gen_helper_VSTRIHR)
static bool trans_VCLRLB(DisasContext *ctx, arg_VX *a)
{
TCGv_i64 rb, mh, ml, tmp,
ones = tcg_constant_i64(-1),
zero = tcg_constant_i64(0);
rb = tcg_temp_new_i64();
mh = tcg_temp_new_i64();
ml = tcg_temp_new_i64();
tmp = tcg_temp_new_i64();
tcg_gen_extu_tl_i64(rb, cpu_gpr[a->vrb]);
tcg_gen_andi_i64(tmp, rb, 7);
tcg_gen_shli_i64(tmp, tmp, 3);
tcg_gen_shl_i64(tmp, ones, tmp);
tcg_gen_not_i64(tmp, tmp);
tcg_gen_movcond_i64(TCG_COND_LTU, ml, rb, tcg_constant_i64(8),
tmp, ones);
tcg_gen_movcond_i64(TCG_COND_LTU, mh, rb, tcg_constant_i64(8),
zero, tmp);
tcg_gen_movcond_i64(TCG_COND_LTU, mh, rb, tcg_constant_i64(16),
mh, ones);
get_avr64(tmp, a->vra, true);
tcg_gen_and_i64(tmp, tmp, mh);
set_avr64(a->vrt, tmp, true);
get_avr64(tmp, a->vra, false);
tcg_gen_and_i64(tmp, tmp, ml);
set_avr64(a->vrt, tmp, false);
tcg_temp_free_i64(rb);
tcg_temp_free_i64(mh);
tcg_temp_free_i64(ml);
tcg_temp_free_i64(tmp);
return true;
}
#define GEN_VAFORM_PAIRED(name0, name1, opc2) \
static void glue(gen_, name0##_##name1)(DisasContext *ctx) \
{ \