sam460ex: Clean up SPD EEPROM creation
Get rid of code from MIPS Malta board used to create SPD EEPROM data (parts of which was not even needed for sam460ex) and use the generic spd_data_generate() function to simplify this. Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
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BALATON Zoltan
David Gibson
parent
b296b664ab
commit
08fd99179a
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@ -2,7 +2,7 @@
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* QEMU aCube Sam460ex board emulation
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*
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* Copyright (c) 2012 François Revol
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* Copyright (c) 2016-2018 BALATON Zoltan
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* Copyright (c) 2016-2019 BALATON Zoltan
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*
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* This file is derived from hw/ppc440_bamboo.c,
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* the copyright for that material belongs to the original owners.
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@ -87,135 +87,6 @@ struct boot_info {
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uint32_t entry;
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};
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/*****************************************************************************/
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/* SPD eeprom content from mips_malta.c */
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struct _eeprom24c0x_t {
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uint8_t tick;
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uint8_t address;
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uint8_t command;
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uint8_t ack;
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uint8_t scl;
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uint8_t sda;
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uint8_t data;
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uint8_t contents[256];
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};
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typedef struct _eeprom24c0x_t eeprom24c0x_t;
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static eeprom24c0x_t spd_eeprom = {
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.contents = {
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/* 00000000: */ 0x80, 0x08, 0xFF, 0x0D, 0x0A, 0xFF, 0x40, 0x00,
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/* 00000008: */ 0x04, 0x75, 0x54, 0x00, 0x82, 0x08, 0x00, 0x01,
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/* 00000010: */ 0x8F, 0x04, 0x02, 0x01, 0x01, 0x00, 0x00, 0x00,
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/* 00000018: */ 0x00, 0x00, 0x00, 0x14, 0x0F, 0x14, 0x2D, 0xFF,
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/* 00000020: */ 0x15, 0x08, 0x15, 0x08, 0x00, 0x00, 0x00, 0x00,
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/* 00000028: */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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/* 00000030: */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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/* 00000038: */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x12, 0xD0,
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/* 00000040: */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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/* 00000048: */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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/* 00000050: */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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/* 00000058: */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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/* 00000060: */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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/* 00000068: */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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/* 00000070: */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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/* 00000078: */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x64, 0xF4,
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},
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};
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static void generate_eeprom_spd(uint8_t *eeprom, ram_addr_t ram_size)
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{
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enum { SDR = 0x4, DDR1 = 0x7, DDR2 = 0x8 } type;
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uint8_t *spd = spd_eeprom.contents;
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uint8_t nbanks = 0;
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uint16_t density = 0;
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int i;
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/* work in terms of MB */
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ram_size /= MiB;
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while ((ram_size >= 4) && (nbanks <= 2)) {
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int sz_log2 = MIN(31 - clz32(ram_size), 14);
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nbanks++;
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density |= 1 << (sz_log2 - 2);
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ram_size -= 1 << sz_log2;
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}
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/* split to 2 banks if possible */
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if ((nbanks == 1) && (density > 1)) {
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nbanks++;
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density >>= 1;
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}
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if (density & 0xff00) {
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density = (density & 0xe0) | ((density >> 8) & 0x1f);
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type = DDR2;
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} else if (!(density & 0x1f)) {
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type = DDR2;
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} else {
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type = SDR;
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}
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if (ram_size) {
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warn_report("SPD cannot represent final " RAM_ADDR_FMT "MB"
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" of SDRAM", ram_size);
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}
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/* fill in SPD memory information */
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spd[2] = type;
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spd[5] = nbanks;
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spd[31] = density;
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/* XXX: this is totally random */
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spd[9] = 0x10; /* CAS tcyc */
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spd[18] = 0x20; /* CAS bit */
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spd[23] = 0x10; /* CAS tcyc */
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spd[25] = 0x10; /* CAS tcyc */
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/* checksum */
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spd[63] = 0;
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for (i = 0; i < 63; i++) {
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spd[63] += spd[i];
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}
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/* copy for SMBUS */
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memcpy(eeprom, spd, sizeof(spd_eeprom.contents));
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}
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static void generate_eeprom_serial(uint8_t *eeprom)
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{
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int i, pos = 0;
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uint8_t mac[6] = { 0x00 };
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uint8_t sn[5] = { 0x01, 0x23, 0x45, 0x67, 0x89 };
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/* version */
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eeprom[pos++] = 0x01;
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/* count */
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eeprom[pos++] = 0x02;
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/* MAC address */
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eeprom[pos++] = 0x01; /* MAC */
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eeprom[pos++] = 0x06; /* length */
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memcpy(&eeprom[pos], mac, sizeof(mac));
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pos += sizeof(mac);
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/* serial number */
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eeprom[pos++] = 0x02; /* serial */
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eeprom[pos++] = 0x05; /* length */
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memcpy(&eeprom[pos], sn, sizeof(sn));
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pos += sizeof(sn);
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/* checksum */
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eeprom[pos] = 0;
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for (i = 0; i < pos; i++) {
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eeprom[pos] += eeprom[i];
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}
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}
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/*****************************************************************************/
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static int sam460ex_load_uboot(void)
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{
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DriveInfo *dinfo;
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@ -393,24 +264,23 @@ static void sam460ex_init(MachineState *machine)
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MemoryRegion *address_space_mem = get_system_memory();
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MemoryRegion *isa = g_new(MemoryRegion, 1);
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MemoryRegion *ram_memories = g_new(MemoryRegion, SDRAM_NR_BANKS);
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hwaddr ram_bases[SDRAM_NR_BANKS];
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hwaddr ram_sizes[SDRAM_NR_BANKS];
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hwaddr ram_bases[SDRAM_NR_BANKS] = {0};
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hwaddr ram_sizes[SDRAM_NR_BANKS] = {0};
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MemoryRegion *l2cache_ram = g_new(MemoryRegion, 1);
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qemu_irq *irqs, *uic[4];
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PCIBus *pci_bus;
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PowerPCCPU *cpu;
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CPUPPCState *env;
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PPC4xxI2CState *i2c[2];
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I2CBus *i2c;
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hwaddr entry = UBOOT_ENTRY;
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hwaddr loadaddr = LOAD_UIMAGE_LOADADDR_INVALID;
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target_long initrd_size = 0;
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DeviceState *dev;
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SysBusDevice *sbdev;
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int success;
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int i;
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struct boot_info *boot_info;
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const size_t smbus_eeprom_size = 8 * 256;
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uint8_t *smbus_eeprom_buf = g_malloc0(smbus_eeprom_size);
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uint8_t *spd_data;
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Error *err = NULL;
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int success;
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cpu = POWERPC_CPU(cpu_create(machine->cpu_type));
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env = &cpu->env;
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@ -439,8 +309,6 @@ static void sam460ex_init(MachineState *machine)
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uic[3] = ppcuic_init(env, &uic[0][16], 0xf0, 0, 1);
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/* SDRAM controller */
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memset(ram_bases, 0, sizeof(ram_bases));
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memset(ram_sizes, 0, sizeof(ram_sizes));
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/* put all RAM on first bank because board has one slot
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* and firmware only checks that */
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machine->ram_size = ppc4xx_sdram_adjust(machine->ram_size, 1,
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@ -451,23 +319,22 @@ static void sam460ex_init(MachineState *machine)
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ppc440_sdram_init(env, SDRAM_NR_BANKS, ram_memories,
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ram_bases, ram_sizes, 1);
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/* generate SPD EEPROM data */
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for (i = 0; i < SDRAM_NR_BANKS; i++) {
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generate_eeprom_spd(&smbus_eeprom_buf[i * 256], ram_sizes[i]);
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}
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generate_eeprom_serial(&smbus_eeprom_buf[4 * 256]);
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generate_eeprom_serial(&smbus_eeprom_buf[6 * 256]);
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/* IIC controllers */
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/* IIC controllers and devices */
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dev = sysbus_create_simple(TYPE_PPC4xx_I2C, 0x4ef600700, uic[0][2]);
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i2c[0] = PPC4xx_I2C(dev);
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object_property_set_bool(OBJECT(dev), true, "realized", NULL);
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smbus_eeprom_init(i2c[0]->bus, 8, smbus_eeprom_buf, smbus_eeprom_size);
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g_free(smbus_eeprom_buf);
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i2c_create_slave(i2c[0]->bus, "m41t80", 0x68);
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i2c = PPC4xx_I2C(dev)->bus;
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/* SPD EEPROM on RAM module */
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spd_data = spd_data_generate(DDR2, ram_sizes[0], &err);
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if (err) {
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warn_report_err(err);
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}
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if (spd_data) {
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spd_data[20] = 4; /* SO-DIMM module */
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smbus_eeprom_init_one(i2c, 0x50, spd_data);
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}
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/* RTC */
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i2c_create_slave(i2c, "m41t80", 0x68);
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dev = sysbus_create_simple(TYPE_PPC4xx_I2C, 0x4ef600800, uic[0][3]);
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i2c[1] = PPC4xx_I2C(dev);
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/* External bus controller */
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ppc405_ebc_init(env);
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