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ppc/pnv: change core mask for POWER9

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When addressed by XSCOM, the first core has the 0x20 chiplet ID but
the CPU PIR can start at 0x0.

Signed-off-by: Cédric Le Goater <clg@kaod.org>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
This commit is contained in:
Cédric Le Goater 2018-01-15 19:04:02 +01:00 committed by David Gibson
parent 83028a2b28
commit 09279d7e7b
2 changed files with 3 additions and 3 deletions
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4
hw/ppc/pnv.c
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@ -707,9 +707,9 @@ static uint32_t pnv_chip_core_pir_p9(PnvChip *chip, uint32_t core_id)
#define POWER8_CORE_MASK (0x7e7eull)
/*
* POWER9 has 24 cores, ids starting at 0x20
* POWER9 has 24 cores, ids starting at 0x0
*/
#define POWER9_CORE_MASK (0xffffff00000000ull)
#define POWER9_CORE_MASK (0xffffffffffffffull)
static void pnv_chip_power8e_class_init(ObjectClass *klass, void *data)
{

2
tests/pnv-xscom-test.c
View File

@ -49,7 +49,7 @@ static const PnvChip pnv_chips[] = {
.xscom_base = 0x000603fc00000000ull,
.xscom_core_base = 0x0ull,
.cfam_id = 0x220d104900008000ull,
.first_core = 0x20,
.first_core = 0x0,
},
#endif
};