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ppc/ppc405: Convert printfs to trace-events

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and one error message to a LOG_GUEST_ERROR.

Signed-off-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20211206103712.1866296-5-clg@kaod.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
This commit is contained in:
Cédric Le Goater 2021-12-17 17:57:17 +01:00
parent de82dabead
commit 09960a5be3
2 changed files with 74 additions and 105 deletions
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159
hw/ppc/ppc405_uc.c
View File

@ -25,6 +25,7 @@
#include "qemu/osdep.h"
#include "qemu/units.h"
#include "qapi/error.h"
#include "qemu/log.h"
#include "cpu.h"
#include "hw/ppc/ppc.h"
#include "hw/i2c/ppc4xx_i2c.h"
@ -38,15 +39,7 @@
#include "hw/intc/ppc-uic.h"
#include "hw/qdev-properties.h"
#include "qapi/error.h"
//#define DEBUG_OPBA
//#define DEBUG_SDRAM
//#define DEBUG_GPIO
//#define DEBUG_SERIAL
//#define DEBUG_OCM
//#define DEBUG_GPT
//#define DEBUG_CLOCKS
//#define DEBUG_CLOCKS_LL
#include "trace.h"
ram_addr_t ppc405_set_bootinfo (CPUPPCState *env, ppc4xx_bd_info_t *bd,
uint32_t flags)
@ -287,13 +280,9 @@ struct ppc4xx_opba_t {
static uint64_t opba_readb(void *opaque, hwaddr addr, unsigned size)
{
ppc4xx_opba_t *opba;
ppc4xx_opba_t *opba = opaque;
uint32_t ret;
#ifdef DEBUG_OPBA
printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr);
#endif
opba = opaque;
switch (addr) {
case 0x00:
ret = opba->cr;
@ -306,19 +295,17 @@ static uint64_t opba_readb(void *opaque, hwaddr addr, unsigned size)
break;
}
trace_opba_readb(addr, ret);
return ret;
}
static void opba_writeb(void *opaque, hwaddr addr, uint64_t value,
unsigned size)
{
ppc4xx_opba_t *opba;
ppc4xx_opba_t *opba = opaque;
trace_opba_writeb(addr, value);
#ifdef DEBUG_OPBA
printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr,
value);
#endif
opba = opaque;
switch (addr) {
case 0x00:
opba->cr = value & 0xF8;
@ -353,10 +340,9 @@ static void ppc4xx_opba_init(hwaddr base)
{
ppc4xx_opba_t *opba;
trace_opba_init(base);
opba = g_malloc0(sizeof(ppc4xx_opba_t));
#ifdef DEBUG_OPBA
printf("%s: offset " TARGET_FMT_plx "\n", __func__, base);
#endif
memory_region_init_io(&opba->io, NULL, &opba_ops, opba, "opba", 0x002);
memory_region_add_subregion(get_system_memory(), base, &opba->io);
qemu_register_reset(ppc4xx_opba_reset, opba);
@ -707,20 +693,14 @@ struct ppc405_gpio_t {
static uint64_t ppc405_gpio_read(void *opaque, hwaddr addr, unsigned size)
{
#ifdef DEBUG_GPIO
printf("%s: addr " TARGET_FMT_plx " size %d\n", __func__, addr, size);
#endif
trace_ppc405_gpio_read(addr, size);
return 0;
}
static void ppc405_gpio_write(void *opaque, hwaddr addr, uint64_t value,
unsigned size)
{
#ifdef DEBUG_GPIO
printf("%s: addr " TARGET_FMT_plx " size %d val %08" PRIx32 "\n",
__func__, addr, size, value);
#endif
trace_ppc405_gpio_write(addr, size, value);
}
static const MemoryRegionOps ppc405_gpio_ops = {
@ -737,10 +717,9 @@ static void ppc405_gpio_init(hwaddr base)
{
ppc405_gpio_t *gpio;
trace_ppc405_gpio_init(base);
gpio = g_malloc0(sizeof(ppc405_gpio_t));
#ifdef DEBUG_GPIO
printf("%s: offset " TARGET_FMT_plx "\n", __func__, base);
#endif
memory_region_init_io(&gpio->io, NULL, &ppc405_gpio_ops, gpio, "pgio", 0x038);
memory_region_add_subregion(get_system_memory(), base, &gpio->io);
qemu_register_reset(&ppc405_gpio_reset, gpio);
@ -770,25 +749,19 @@ static void ocm_update_mappings (ppc405_ocm_t *ocm,
uint32_t isarc, uint32_t isacntl,
uint32_t dsarc, uint32_t dsacntl)
{
#ifdef DEBUG_OCM
printf("OCM update ISA %08" PRIx32 " %08" PRIx32 " (%08" PRIx32
" %08" PRIx32 ") DSA %08" PRIx32 " %08" PRIx32
" (%08" PRIx32 " %08" PRIx32 ")\n",
isarc, isacntl, dsarc, dsacntl,
ocm->isarc, ocm->isacntl, ocm->dsarc, ocm->dsacntl);
#endif
trace_ocm_update_mappings(isarc, isacntl, dsarc, dsacntl, ocm->isarc,
ocm->isacntl, ocm->dsarc, ocm->dsacntl);
if (ocm->isarc != isarc ||
(ocm->isacntl & 0x80000000) != (isacntl & 0x80000000)) {
if (ocm->isacntl & 0x80000000) {
/* Unmap previously assigned memory region */
printf("OCM unmap ISA %08" PRIx32 "\n", ocm->isarc);
trace_ocm_unmap("ISA", ocm->isarc);
memory_region_del_subregion(get_system_memory(), &ocm->isarc_ram);
}
if (isacntl & 0x80000000) {
/* Map new instruction memory region */
#ifdef DEBUG_OCM
printf("OCM map ISA %08" PRIx32 "\n", isarc);
#endif
trace_ocm_map("ISA", isarc);
memory_region_add_subregion(get_system_memory(), isarc,
&ocm->isarc_ram);
}
@ -799,9 +772,7 @@ static void ocm_update_mappings (ppc405_ocm_t *ocm,
/* Beware not to unmap the region we just mapped */
if (!(isacntl & 0x80000000) || ocm->dsarc != isarc) {
/* Unmap previously assigned memory region */
#ifdef DEBUG_OCM
printf("OCM unmap DSA %08" PRIx32 "\n", ocm->dsarc);
#endif
trace_ocm_unmap("DSA", ocm->dsarc);
memory_region_del_subregion(get_system_memory(),
&ocm->dsarc_ram);
}
@ -810,9 +781,7 @@ static void ocm_update_mappings (ppc405_ocm_t *ocm,
/* Beware not to remap the region we just mapped */
if (!(isacntl & 0x80000000) || dsarc != isarc) {
/* Map new data memory region */
#ifdef DEBUG_OCM
printf("OCM map DSA %08" PRIx32 "\n", dsarc);
#endif
trace_ocm_map("DSA", dsarc);
memory_region_add_subregion(get_system_memory(), dsarc,
&ocm->dsarc_ram);
}
@ -988,14 +957,12 @@ static void ppc4xx_gpt_compute_timer (ppc4xx_gpt_t *gpt)
static uint64_t ppc4xx_gpt_read(void *opaque, hwaddr addr, unsigned size)
{
ppc4xx_gpt_t *gpt;
ppc4xx_gpt_t *gpt = opaque;
uint32_t ret;
int idx;
#ifdef DEBUG_GPT
printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr);
#endif
gpt = opaque;
trace_ppc4xx_gpt_read(addr, size);
switch (addr) {
case 0x00:
/* Time base counter */
@ -1044,14 +1011,11 @@ static uint64_t ppc4xx_gpt_read(void *opaque, hwaddr addr, unsigned size)
static void ppc4xx_gpt_write(void *opaque, hwaddr addr, uint64_t value,
unsigned size)
{
ppc4xx_gpt_t *gpt;
ppc4xx_gpt_t *gpt = opaque;
int idx;
#ifdef DEBUG_I2C
printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr,
value);
#endif
gpt = opaque;
trace_ppc4xx_gpt_write(addr, size, value);
switch (addr) {
case 0x00:
/* Time base counter */
@ -1144,14 +1108,13 @@ static void ppc4xx_gpt_init(hwaddr base, qemu_irq irqs[5])
ppc4xx_gpt_t *gpt;
int i;
trace_ppc4xx_gpt_init(base);
gpt = g_malloc0(sizeof(ppc4xx_gpt_t));
for (i = 0; i < 5; i++) {
gpt->irqs[i] = irqs[i];
}
gpt->timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, &ppc4xx_gpt_cb, gpt);
#ifdef DEBUG_GPT
printf("%s: offset " TARGET_FMT_plx "\n", __func__, base);
#endif
memory_region_init_io(&gpt->iomem, NULL, &gpt_ops, gpt, "gpt", 0x0d4);
memory_region_add_subregion(get_system_memory(), base, &gpt->iomem);
qemu_register_reset(ppc4xx_gpt_reset, gpt);
@ -1215,17 +1178,14 @@ static void ppc405ep_compute_clocks (ppc405ep_cpc_t *cpc)
VCO_out = 0;
if ((cpc->pllmr[1] & 0x80000000) && !(cpc->pllmr[1] & 0x40000000)) {
M = (((cpc->pllmr[1] >> 20) - 1) & 0xF) + 1; /* FBMUL */
#ifdef DEBUG_CLOCKS_LL
printf("FBMUL %01" PRIx32 " %d\n", (cpc->pllmr[1] >> 20) & 0xF, M);
#endif
trace_ppc405ep_clocks_compute("FBMUL", (cpc->pllmr[1] >> 20) & 0xF, M);
D = 8 - ((cpc->pllmr[1] >> 16) & 0x7); /* FWDA */
#ifdef DEBUG_CLOCKS_LL
printf("FWDA %01" PRIx32 " %d\n", (cpc->pllmr[1] >> 16) & 0x7, D);
#endif
trace_ppc405ep_clocks_compute("FWDA", (cpc->pllmr[1] >> 16) & 0x7, D);
VCO_out = (uint64_t)cpc->sysclk * M * D;
if (VCO_out < 500000000UL || VCO_out > 1000000000UL) {
/* Error - unlock the PLL */
printf("VCO out of range %" PRIu64 "\n", VCO_out);
qemu_log_mask(LOG_GUEST_ERROR, "VCO out of range %" PRIu64 "\n",
VCO_out);
#if 0
cpc->pllmr[1] &= ~0x80000000;
goto pll_bypass;
@ -1246,54 +1206,43 @@ static void ppc405ep_compute_clocks (ppc405ep_cpc_t *cpc)
}
/* Now, compute all other clocks */
D = ((cpc->pllmr[0] >> 20) & 0x3) + 1; /* CCDV */
#ifdef DEBUG_CLOCKS_LL
printf("CCDV %01" PRIx32 " %d\n", (cpc->pllmr[0] >> 20) & 0x3, D);
#endif
trace_ppc405ep_clocks_compute("CCDV", (cpc->pllmr[0] >> 20) & 0x3, D);
CPU_clk = PLL_out / D;
D = ((cpc->pllmr[0] >> 16) & 0x3) + 1; /* CBDV */
#ifdef DEBUG_CLOCKS_LL
printf("CBDV %01" PRIx32 " %d\n", (cpc->pllmr[0] >> 16) & 0x3, D);
#endif
trace_ppc405ep_clocks_compute("CBDV", (cpc->pllmr[0] >> 16) & 0x3, D);
PLB_clk = CPU_clk / D;
D = ((cpc->pllmr[0] >> 12) & 0x3) + 1; /* OPDV */
#ifdef DEBUG_CLOCKS_LL
printf("OPDV %01" PRIx32 " %d\n", (cpc->pllmr[0] >> 12) & 0x3, D);
#endif
trace_ppc405ep_clocks_compute("OPDV", (cpc->pllmr[0] >> 12) & 0x3, D);
OPB_clk = PLB_clk / D;
D = ((cpc->pllmr[0] >> 8) & 0x3) + 2; /* EPDV */
#ifdef DEBUG_CLOCKS_LL
printf("EPDV %01" PRIx32 " %d\n", (cpc->pllmr[0] >> 8) & 0x3, D);
#endif
trace_ppc405ep_clocks_compute("EPDV", (cpc->pllmr[0] >> 8) & 0x3, D);
EBC_clk = PLB_clk / D;
D = ((cpc->pllmr[0] >> 4) & 0x3) + 1; /* MPDV */
#ifdef DEBUG_CLOCKS_LL
printf("MPDV %01" PRIx32 " %d\n", (cpc->pllmr[0] >> 4) & 0x3, D);
#endif
trace_ppc405ep_clocks_compute("MPDV", (cpc->pllmr[0] >> 4) & 0x3, D);
MAL_clk = PLB_clk / D;
D = (cpc->pllmr[0] & 0x3) + 1; /* PPDV */
#ifdef DEBUG_CLOCKS_LL
printf("PPDV %01" PRIx32 " %d\n", cpc->pllmr[0] & 0x3, D);
#endif
trace_ppc405ep_clocks_compute("PPDV", cpc->pllmr[0] & 0x3, D);
PCI_clk = PLB_clk / D;
D = ((cpc->ucr - 1) & 0x7F) + 1; /* U0DIV */
#ifdef DEBUG_CLOCKS_LL
printf("U0DIV %01" PRIx32 " %d\n", cpc->ucr & 0x7F, D);
#endif
trace_ppc405ep_clocks_compute("U0DIV", cpc->ucr & 0x7F, D);
UART0_clk = PLL_out / D;
D = (((cpc->ucr >> 8) - 1) & 0x7F) + 1; /* U1DIV */
#ifdef DEBUG_CLOCKS_LL
printf("U1DIV %01" PRIx32 " %d\n", (cpc->ucr >> 8) & 0x7F, D);
#endif
trace_ppc405ep_clocks_compute("U1DIV", (cpc->ucr >> 8) & 0x7F, D);
UART1_clk = PLL_out / D;
#ifdef DEBUG_CLOCKS
printf("Setup PPC405EP clocks - sysclk %" PRIu32 " VCO %" PRIu64
" PLL out %" PRIu64 " Hz\n", cpc->sysclk, VCO_out, PLL_out);
printf("CPU %" PRIu32 " PLB %" PRIu32 " OPB %" PRIu32 " EBC %" PRIu32
" MAL %" PRIu32 " PCI %" PRIu32 " UART0 %" PRIu32
" UART1 %" PRIu32 "\n",
CPU_clk, PLB_clk, OPB_clk, EBC_clk, MAL_clk, PCI_clk,
UART0_clk, UART1_clk);
#endif
if (trace_event_get_state_backends(TRACE_PPC405EP_CLOCKS_SETUP)) {
g_autofree char *trace = g_strdup_printf(
"Setup PPC405EP clocks - sysclk %" PRIu32 " VCO %" PRIu64
" PLL out %" PRIu64 " Hz\n"
"CPU %" PRIu32 " PLB %" PRIu32 " OPB %" PRIu32 " EBC %" PRIu32
" MAL %" PRIu32 " PCI %" PRIu32 " UART0 %" PRIu32
" UART1 %" PRIu32 "\n",
cpc->sysclk, VCO_out, PLL_out,
CPU_clk, PLB_clk, OPB_clk, EBC_clk, MAL_clk, PCI_clk,
UART0_clk, UART1_clk);
trace_ppc405ep_clocks_setup(trace);
}
/* Setup CPU clocks */
clk_setup(&cpc->clk_setup[PPC405EP_CPU_CLK], CPU_clk);
/* Setup PLB clock */

20
hw/ppc/trace-events
View File

@ -144,3 +144,23 @@ ppc440_pcix_update_pim(int idx, uint64_t size, uint64_t la) "Added window %d of
ppc440_pcix_update_pom(int idx, uint32_t size, uint64_t la, uint64_t pcia) "Added window %d of size=0x%x from CPU=0x%" PRIx64 " to PCI=0x%" PRIx64
ppc440_pcix_reg_read(uint64_t addr, uint32_t val) "addr 0x%" PRIx64 " = 0x%" PRIx32
ppc440_pcix_reg_write(uint64_t addr, uint32_t val, uint32_t size) "addr 0x%" PRIx64 " = 0x%" PRIx32 " size 0x%" PRIx32
# ppc405_boards.c
opba_readb(uint64_t addr, uint32_t val) "addr 0x%" PRIx64 " = 0x%" PRIx32
opba_writeb(uint64_t addr, uint64_t val) "addr 0x%" PRIx64 " = 0x%" PRIx64
opba_init(uint64_t addr) "offet 0x%" PRIx64
ppc405_gpio_read(uint64_t addr, uint32_t size) "addr 0x%" PRIx64 " size %d"
ppc405_gpio_write(uint64_t addr, uint32_t size, uint64_t val) "addr 0x%" PRIx64 " size %d = 0x%" PRIx64
ppc405_gpio_init(uint64_t addr) "offet 0x%" PRIx64
ocm_update_mappings(uint32_t isarc, uint32_t isacntl, uint32_t dsarc, uint32_t dsacntl, uint32_t ocm_isarc, uint32_t ocm_isacntl, uint32_t ocm_dsarc, uint32_t ocm_dsacntl) "OCM update ISA 0x%08" PRIx32 " 0x%08" PRIx32 " (0x%08" PRIx32" 0x%08" PRIx32 ") DSA 0x%08" PRIx32 " 0x%08" PRIx32" (0x%08" PRIx32 " 0x%08" PRIx32 ")"
ocm_map(const char* prefix, uint32_t isarc) "OCM map %s 0x%08" PRIx32
ocm_unmap(const char* prefix, uint32_t isarc) "OCM unmap %s 0x%08" PRIx32
ppc4xx_gpt_read(uint64_t addr, uint32_t size) "addr 0x%" PRIx64 " size %d"
ppc4xx_gpt_write(uint64_t addr, uint32_t size, uint64_t val) "addr 0x%" PRIx64 " size %d = 0x%" PRIx64
ppc4xx_gpt_init(uint64_t addr) "offet 0x%" PRIx64
ppc405ep_clocks_compute(const char *param, uint32_t param2, uint32_t val) "%s 0x%1" PRIx32 " %d"
ppc405ep_clocks_setup(const char *trace) "%s"