target-arm: A64: Add saturating accumulate ops (USQADD/SUQADD)
Add the saturating accumulate operations USQADD and SUQADD to the A64 instruction set. This completes coverage of A64 Neon. These operations (which are unsigned + signed -> signed and signed + unsigned -> unsigned) don't exist in the A32/T32 instruction set, so require a complete new set of helper functions. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <rth@twiddle.net>
This commit is contained in:
Alex Bennée
Peter Maydell
parent
0a79bc87c3
commit
09e037354b
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@ -186,12 +186,20 @@ DEF_HELPER_FLAGS_2(rints, TCG_CALL_NO_RWG, f32, f32, ptr)
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DEF_HELPER_FLAGS_2(rintd, TCG_CALL_NO_RWG, f64, f64, ptr)
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/* neon_helper.c */
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DEF_HELPER_3(neon_qadd_u8, i32, env, i32, i32)
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DEF_HELPER_3(neon_qadd_s8, i32, env, i32, i32)
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DEF_HELPER_3(neon_qadd_u16, i32, env, i32, i32)
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DEF_HELPER_3(neon_qadd_s16, i32, env, i32, i32)
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DEF_HELPER_3(neon_qadd_u32, i32, env, i32, i32)
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DEF_HELPER_3(neon_qadd_s32, i32, env, i32, i32)
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DEF_HELPER_FLAGS_3(neon_qadd_u8, TCG_CALL_NO_RWG, i32, env, i32, i32)
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DEF_HELPER_FLAGS_3(neon_qadd_s8, TCG_CALL_NO_RWG, i32, env, i32, i32)
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DEF_HELPER_FLAGS_3(neon_qadd_u16, TCG_CALL_NO_RWG, i32, env, i32, i32)
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DEF_HELPER_FLAGS_3(neon_qadd_s16, TCG_CALL_NO_RWG, i32, env, i32, i32)
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DEF_HELPER_FLAGS_3(neon_qadd_u32, TCG_CALL_NO_RWG, i32, env, i32, i32)
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DEF_HELPER_FLAGS_3(neon_qadd_s32, TCG_CALL_NO_RWG, i32, env, i32, i32)
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DEF_HELPER_FLAGS_3(neon_uqadd_s8, TCG_CALL_NO_RWG, i32, env, i32, i32)
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DEF_HELPER_FLAGS_3(neon_uqadd_s16, TCG_CALL_NO_RWG, i32, env, i32, i32)
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DEF_HELPER_FLAGS_3(neon_uqadd_s32, TCG_CALL_NO_RWG, i32, env, i32, i32)
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DEF_HELPER_FLAGS_3(neon_uqadd_s64, TCG_CALL_NO_RWG, i64, env, i64, i64)
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DEF_HELPER_FLAGS_3(neon_sqadd_u8, TCG_CALL_NO_RWG, i32, env, i32, i32)
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DEF_HELPER_FLAGS_3(neon_sqadd_u16, TCG_CALL_NO_RWG, i32, env, i32, i32)
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DEF_HELPER_FLAGS_3(neon_sqadd_u32, TCG_CALL_NO_RWG, i32, env, i32, i32)
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DEF_HELPER_FLAGS_3(neon_sqadd_u64, TCG_CALL_NO_RWG, i64, env, i64, i64)
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DEF_HELPER_3(neon_qsub_u8, i32, env, i32, i32)
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DEF_HELPER_3(neon_qsub_s8, i32, env, i32, i32)
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DEF_HELPER_3(neon_qsub_u16, i32, env, i32, i32)
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@ -236,6 +236,171 @@ uint64_t HELPER(neon_qadd_s64)(CPUARMState *env, uint64_t src1, uint64_t src2)
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return res;
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}
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/* Unsigned saturating accumulate of signed value
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*
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* Op1/Rn is treated as signed
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* Op2/Rd is treated as unsigned
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*
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* Explicit casting is used to ensure the correct sign extension of
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* inputs. The result is treated as a unsigned value and saturated as such.
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*
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* We use a macro for the 8/16 bit cases which expects signed integers of va,
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* vb, and vr for interim calculation and an unsigned 32 bit result value r.
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*/
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#define USATACC(bits, shift) \
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do { \
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va = sextract32(a, shift, bits); \
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vb = extract32(b, shift, bits); \
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vr = va + vb; \
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if (vr > UINT##bits##_MAX) { \
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SET_QC(); \
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vr = UINT##bits##_MAX; \
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} else if (vr < 0) { \
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SET_QC(); \
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vr = 0; \
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} \
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r = deposit32(r, shift, bits, vr); \
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} while (0)
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uint32_t HELPER(neon_uqadd_s8)(CPUARMState *env, uint32_t a, uint32_t b)
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{
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int16_t va, vb, vr;
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uint32_t r = 0;
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USATACC(8, 0);
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USATACC(8, 8);
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USATACC(8, 16);
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USATACC(8, 24);
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return r;
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}
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uint32_t HELPER(neon_uqadd_s16)(CPUARMState *env, uint32_t a, uint32_t b)
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{
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int32_t va, vb, vr;
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uint64_t r = 0;
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USATACC(16, 0);
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USATACC(16, 16);
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return r;
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}
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#undef USATACC
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uint32_t HELPER(neon_uqadd_s32)(CPUARMState *env, uint32_t a, uint32_t b)
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{
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int64_t va = (int32_t)a;
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int64_t vb = (uint32_t)b;
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int64_t vr = va + vb;
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if (vr > UINT32_MAX) {
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SET_QC();
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vr = UINT32_MAX;
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} else if (vr < 0) {
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SET_QC();
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vr = 0;
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}
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return vr;
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}
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uint64_t HELPER(neon_uqadd_s64)(CPUARMState *env, uint64_t a, uint64_t b)
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{
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uint64_t res;
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res = a + b;
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/* We only need to look at the pattern of SIGN bits to detect
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* +ve/-ve saturation
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*/
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if (~a & b & ~res & SIGNBIT64) {
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SET_QC();
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res = UINT64_MAX;
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} else if (a & ~b & res & SIGNBIT64) {
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SET_QC();
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res = 0;
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}
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return res;
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}
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/* Signed saturating accumulate of unsigned value
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*
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* Op1/Rn is treated as unsigned
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* Op2/Rd is treated as signed
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*
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* The result is treated as a signed value and saturated as such
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*
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* We use a macro for the 8/16 bit cases which expects signed integers of va,
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* vb, and vr for interim calculation and an unsigned 32 bit result value r.
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*/
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#define SSATACC(bits, shift) \
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do { \
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va = extract32(a, shift, bits); \
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vb = sextract32(b, shift, bits); \
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vr = va + vb; \
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if (vr > INT##bits##_MAX) { \
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SET_QC(); \
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vr = INT##bits##_MAX; \
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} else if (vr < INT##bits##_MIN) { \
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SET_QC(); \
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vr = INT##bits##_MIN; \
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} \
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r = deposit32(r, shift, bits, vr); \
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} while (0)
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uint32_t HELPER(neon_sqadd_u8)(CPUARMState *env, uint32_t a, uint32_t b)
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{
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int16_t va, vb, vr;
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uint32_t r = 0;
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SSATACC(8, 0);
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SSATACC(8, 8);
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SSATACC(8, 16);
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SSATACC(8, 24);
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return r;
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}
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uint32_t HELPER(neon_sqadd_u16)(CPUARMState *env, uint32_t a, uint32_t b)
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{
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int32_t va, vb, vr;
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uint32_t r = 0;
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SSATACC(16, 0);
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SSATACC(16, 16);
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return r;
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}
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#undef SSATACC
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uint32_t HELPER(neon_sqadd_u32)(CPUARMState *env, uint32_t a, uint32_t b)
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{
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int64_t res;
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int64_t op1 = (uint32_t)a;
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int64_t op2 = (int32_t)b;
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res = op1 + op2;
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if (res > INT32_MAX) {
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SET_QC();
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res = INT32_MAX;
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} else if (res < INT32_MIN) {
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SET_QC();
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res = INT32_MIN;
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}
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return res;
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}
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uint64_t HELPER(neon_sqadd_u64)(CPUARMState *env, uint64_t a, uint64_t b)
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{
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uint64_t res;
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res = a + b;
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/* We only need to look at the pattern of SIGN bits to detect an overflow */
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if (((a & res)
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| (~b & res)
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SET_QC();
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res = INT64_MAX;
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}
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return res;
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}
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#define NEON_USAT(dest, src1, src2, type) do { \
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uint32_t tmp = (uint32_t)src1 - (uint32_t)src2; \
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if (tmp != (type)tmp) { \
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@ -7321,6 +7321,101 @@ static void handle_2misc_narrow(DisasContext *s, bool scalar,
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}
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}
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/* Remaining saturating accumulating ops */
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static void handle_2misc_satacc(DisasContext *s, bool is_scalar, bool is_u,
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bool is_q, int size, int rn, int rd)
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{
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bool is_double = (size == 3);
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if (is_double) {
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TCGv_i64 tcg_rn = tcg_temp_new_i64();
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TCGv_i64 tcg_rd = tcg_temp_new_i64();
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int pass;
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for (pass = 0; pass < (is_scalar ? 1 : 2); pass++) {
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read_vec_element(s, tcg_rn, rn, pass, MO_64);
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read_vec_element(s, tcg_rd, rd, pass, MO_64);
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if (is_u) { /* USQADD */
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gen_helper_neon_uqadd_s64(tcg_rd, cpu_env, tcg_rn, tcg_rd);
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} else { /* SUQADD */
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gen_helper_neon_sqadd_u64(tcg_rd, cpu_env, tcg_rn, tcg_rd);
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}
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write_vec_element(s, tcg_rd, rd, pass, MO_64);
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}
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if (is_scalar) {
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clear_vec_high(s, rd);
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}
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tcg_temp_free_i64(tcg_rd);
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tcg_temp_free_i64(tcg_rn);
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} else {
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TCGv_i32 tcg_rn = tcg_temp_new_i32();
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TCGv_i32 tcg_rd = tcg_temp_new_i32();
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int pass, maxpasses;
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if (is_scalar) {
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maxpasses = 1;
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} else {
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maxpasses = is_q ? 4 : 2;
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}
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for (pass = 0; pass < maxpasses; pass++) {
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if (is_scalar) {
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read_vec_element_i32(s, tcg_rn, rn, pass, size);
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read_vec_element_i32(s, tcg_rd, rd, pass, size);
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} else {
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read_vec_element_i32(s, tcg_rn, rn, pass, MO_32);
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read_vec_element_i32(s, tcg_rd, rd, pass, MO_32);
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}
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if (is_u) { /* USQADD */
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switch (size) {
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case 0:
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gen_helper_neon_uqadd_s8(tcg_rd, cpu_env, tcg_rn, tcg_rd);
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break;
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case 1:
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gen_helper_neon_uqadd_s16(tcg_rd, cpu_env, tcg_rn, tcg_rd);
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break;
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case 2:
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gen_helper_neon_uqadd_s32(tcg_rd, cpu_env, tcg_rn, tcg_rd);
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break;
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default:
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g_assert_not_reached();
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}
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} else { /* SUQADD */
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switch (size) {
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case 0:
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gen_helper_neon_sqadd_u8(tcg_rd, cpu_env, tcg_rn, tcg_rd);
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break;
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case 1:
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gen_helper_neon_sqadd_u16(tcg_rd, cpu_env, tcg_rn, tcg_rd);
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break;
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case 2:
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gen_helper_neon_sqadd_u32(tcg_rd, cpu_env, tcg_rn, tcg_rd);
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break;
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default:
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g_assert_not_reached();
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}
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}
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if (is_scalar) {
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TCGv_i64 tcg_zero = tcg_const_i64(0);
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write_vec_element(s, tcg_zero, rd, 0, MO_64);
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tcg_temp_free_i64(tcg_zero);
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}
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write_vec_element_i32(s, tcg_rd, rd, pass, MO_32);
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}
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if (!is_q) {
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clear_vec_high(s, rd);
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}
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tcg_temp_free_i32(tcg_rd);
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tcg_temp_free_i32(tcg_rn);
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}
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}
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/* C3.6.12 AdvSIMD scalar two reg misc
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* 31 30 29 28 24 23 22 21 17 16 12 11 10 9 5 4 0
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* +-----+---+-----------+------+-----------+--------+-----+------+------+
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@ -7340,6 +7435,9 @@ static void disas_simd_scalar_two_reg_misc(DisasContext *s, uint32_t insn)
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TCGv_ptr tcg_fpstatus;
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switch (opcode) {
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case 0x3: /* USQADD / SUQADD*/
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handle_2misc_satacc(s, true, u, false, size, rn, rd);
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return;
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case 0x7: /* SQABS / SQNEG */
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break;
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case 0xa: /* CMLT */
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@ -7427,10 +7525,7 @@ static void disas_simd_scalar_two_reg_misc(DisasContext *s, uint32_t insn)
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}
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break;
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default:
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/* Other categories of encoding in this class:
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* + SUQADD/USQADD/SQABS/SQNEG : size 8, 16, 32 or 64
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*/
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unsupported_encoding(s, insn);
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unallocated_encoding(s);
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return;
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}
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@ -9194,6 +9289,12 @@ static void disas_simd_two_reg_misc(DisasContext *s, uint32_t insn)
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}
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break;
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case 0x3: /* SUQADD, USQADD */
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if (size == 3 && !is_q) {
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unallocated_encoding(s);
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return;
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}
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handle_2misc_satacc(s, false, u, is_q, size, rn, rd);
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return;
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case 0x7: /* SQABS, SQNEG */
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if (size == 3 && !is_q) {
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unallocated_encoding(s);
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