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target/nios2: Use hw/registerfields.h for CR_TLBADDR fields 

Use FIELD_EX32 and FIELD_DP32 instead of manual manipulation
of the fields.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20220421151735.31996-27-richard.henderson@linaro.org>
This commit is contained in:
Richard Henderson 2022-04-21 08:16:57 -07:00
parent bf754c96b2
commit 0a1fc63043
4 changed files with 16 additions and 15 deletions
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8
target/nios2/cpu.h
View File

@ -110,10 +110,10 @@ FIELD(CR_EXCEPTION, CAUSE, 2, 5)
FIELD(CR_EXCEPTION, ECCFTL, 31, 1) FIELD(CR_EXCEPTION, ECCFTL, 31, 1)
#define CR_PTEADDR 8 #define CR_PTEADDR 8
#define CR_PTEADDR_PTBASE_SHIFT 22
#define CR_PTEADDR_PTBASE_MASK (0x3FF << CR_PTEADDR_PTBASE_SHIFT) FIELD(CR_PTEADDR, VPN, 2, 20)
#define CR_PTEADDR_VPN_SHIFT 2 FIELD(CR_PTEADDR, PTBASE, 22, 10)
#define CR_PTEADDR_VPN_MASK (0xFFFFF << CR_PTEADDR_VPN_SHIFT)
#define CR_TLBACC 9 #define CR_TLBACC 9
#define CR_TLBACC_IGN_SHIFT 25 #define CR_TLBACC_IGN_SHIFT 25
#define CR_TLBACC_IGN_MASK (0x7F << CR_TLBACC_IGN_SHIFT) #define CR_TLBACC_IGN_MASK (0x7F << CR_TLBACC_IGN_SHIFT)

4
target/nios2/helper.c
View File

@ -286,8 +286,8 @@ bool nios2_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
} else { } else {
env->ctrl[CR_TLBMISC] |= CR_TLBMISC_D; env->ctrl[CR_TLBMISC] |= CR_TLBMISC_D;
} }
env->ctrl[CR_PTEADDR] &= CR_PTEADDR_PTBASE_MASK; env->ctrl[CR_PTEADDR] = FIELD_DP32(env->ctrl[CR_PTEADDR], CR_PTEADDR, VPN,
env->ctrl[CR_PTEADDR] |= (address >> 10) & CR_PTEADDR_VPN_MASK; address >> TARGET_PAGE_BITS);
env->mmu.pteaddr_wr = env->ctrl[CR_PTEADDR]; env->mmu.pteaddr_wr = env->ctrl[CR_PTEADDR];
cs->exception_index = excp; cs->exception_index = excp;

17
target/nios2/mmu.c
View File

@ -97,7 +97,7 @@ void helper_mmu_write_tlbacc(CPUNios2State *env, uint32_t v)
/* if tlbmisc.WE == 1 then trigger a TLB write on writes to TLBACC */ /* if tlbmisc.WE == 1 then trigger a TLB write on writes to TLBACC */
if (env->ctrl[CR_TLBMISC] & CR_TLBMISC_WR) { if (env->ctrl[CR_TLBMISC] & CR_TLBMISC_WR) {
int way = (env->ctrl[CR_TLBMISC] >> CR_TLBMISC_WAY_SHIFT); int way = (env->ctrl[CR_TLBMISC] >> CR_TLBMISC_WAY_SHIFT);
int vpn = (env->mmu.pteaddr_wr & CR_PTEADDR_VPN_MASK) >> 2; int vpn = FIELD_EX32(env->mmu.pteaddr_wr, CR_PTEADDR, VPN);
int pid = (env->mmu.tlbmisc_wr & CR_TLBMISC_PID_MASK) >> 4; int pid = (env->mmu.tlbmisc_wr & CR_TLBMISC_PID_MASK) >> 4;
int g = (v & CR_TLBACC_G) ? 1 : 0; int g = (v & CR_TLBACC_G) ? 1 : 0;
int valid = ((vpn & CR_TLBACC_PFN_MASK) < 0xC0000) ? 1 : 0; int valid = ((vpn & CR_TLBACC_PFN_MASK) < 0xC0000) ? 1 : 0;
@ -148,7 +148,7 @@ void helper_mmu_write_tlbmisc(CPUNios2State *env, uint32_t v)
/* if tlbmisc.RD == 1 then trigger a TLB read on writes to TLBMISC */ /* if tlbmisc.RD == 1 then trigger a TLB read on writes to TLBMISC */
if (v & CR_TLBMISC_RD) { if (v & CR_TLBMISC_RD) {
int way = (v >> CR_TLBMISC_WAY_SHIFT); int way = (v >> CR_TLBMISC_WAY_SHIFT);
int vpn = (env->mmu.pteaddr_wr & CR_PTEADDR_VPN_MASK) >> 2; int vpn = FIELD_EX32(env->mmu.pteaddr_wr, CR_PTEADDR, VPN);
Nios2TLBEntry *entry = Nios2TLBEntry *entry =
&env->mmu.tlb[(way * cpu->tlb_num_ways) + &env->mmu.tlb[(way * cpu->tlb_num_ways) +
(vpn & env->mmu.tlb_entry_mask)]; (vpn & env->mmu.tlb_entry_mask)];
@ -160,8 +160,9 @@ void helper_mmu_write_tlbmisc(CPUNios2State *env, uint32_t v)
(v & ~CR_TLBMISC_PID_MASK) | (v & ~CR_TLBMISC_PID_MASK) |
((entry->tag & ((1 << cpu->pid_num_bits) - 1)) << ((entry->tag & ((1 << cpu->pid_num_bits) - 1)) <<
CR_TLBMISC_PID_SHIFT); CR_TLBMISC_PID_SHIFT);
env->ctrl[CR_PTEADDR] &= ~CR_PTEADDR_VPN_MASK; env->ctrl[CR_PTEADDR] = FIELD_DP32(env->ctrl[CR_PTEADDR],
env->ctrl[CR_PTEADDR] |= (entry->tag >> 12) << CR_PTEADDR_VPN_SHIFT; CR_PTEADDR, VPN,
entry->tag >> TARGET_PAGE_BITS);
} else { } else {
env->ctrl[CR_TLBMISC] = v; env->ctrl[CR_TLBMISC] = v;
} }
@ -171,12 +172,12 @@ void helper_mmu_write_tlbmisc(CPUNios2State *env, uint32_t v)
void helper_mmu_write_pteaddr(CPUNios2State *env, uint32_t v) void helper_mmu_write_pteaddr(CPUNios2State *env, uint32_t v)
{ {
trace_nios2_mmu_write_pteaddr(v >> CR_PTEADDR_PTBASE_SHIFT, trace_nios2_mmu_write_pteaddr(FIELD_EX32(v, CR_PTEADDR, PTBASE),
(v & CR_PTEADDR_VPN_MASK) >> CR_PTEADDR_VPN_SHIFT); FIELD_EX32(v, CR_PTEADDR, VPN));
/* Writes to PTEADDR don't change the read-back VPN value */ /* Writes to PTEADDR don't change the read-back VPN value */
env->ctrl[CR_PTEADDR] = ((v & ~CR_PTEADDR_VPN_MASK) | env->ctrl[CR_PTEADDR] = ((v & ~R_CR_PTEADDR_VPN_MASK) |
(env->ctrl[CR_PTEADDR] & CR_PTEADDR_VPN_MASK)); (env->ctrl[CR_PTEADDR] & R_CR_PTEADDR_VPN_MASK));
env->mmu.pteaddr_wr = v; env->mmu.pteaddr_wr = v;
} }

2
target/nios2/translate.c
View File

@ -924,7 +924,7 @@ void nios2_cpu_dump_state(CPUState *cs, FILE *f, int flags)
} }
} }
qemu_fprintf(f, " mmu write: VPN=%05X PID %02X TLBACC %08X\n", qemu_fprintf(f, " mmu write: VPN=%05X PID %02X TLBACC %08X\n",
env->mmu.pteaddr_wr & CR_PTEADDR_VPN_MASK, env->mmu.pteaddr_wr & R_CR_PTEADDR_VPN_MASK,
(env->mmu.tlbmisc_wr & CR_TLBMISC_PID_MASK) >> 4, (env->mmu.tlbmisc_wr & CR_TLBMISC_PID_MASK) >> 4,
env->mmu.tlbacc_wr); env->mmu.tlbacc_wr);
#endif #endif