OpenE2K/qemu-e2k
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hw/riscv: use qemu_configure_nic_device()

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Signed-off-by: David Woodhouse <dwmw@amazon.co.uk>
Reviewed-by: Thomas Huth <thuth@redhat.com>
This commit is contained in:
David Woodhouse 2023-10-23 09:37:53 +01:00
parent 5fcc51548d
commit 0a7549db03
2 changed files with 3 additions and 18 deletions
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14
hw/riscv/microchip_pfsoc.c
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@ -202,7 +202,6 @@ static void microchip_pfsoc_soc_realize(DeviceState *dev, Error **errp)
MemoryRegion *envm_data = g_new(MemoryRegion, 1); MemoryRegion *envm_data = g_new(MemoryRegion, 1);
MemoryRegion *qspi_xip_mem = g_new(MemoryRegion, 1); MemoryRegion *qspi_xip_mem = g_new(MemoryRegion, 1);
char *plic_hart_config; char *plic_hart_config;
NICInfo *nd;
int i; int i;
sysbus_realize(SYS_BUS_DEVICE(&s->e_cpus), &error_abort); sysbus_realize(SYS_BUS_DEVICE(&s->e_cpus), &error_abort);
@ -411,17 +410,8 @@ static void microchip_pfsoc_soc_realize(DeviceState *dev, Error **errp)
memmap[MICROCHIP_PFSOC_USB].size); memmap[MICROCHIP_PFSOC_USB].size);
/* GEMs */ /* GEMs */
qemu_configure_nic_device(DEVICE(&s->gem0), true, NULL);
nd = &nd_table[0]; qemu_configure_nic_device(DEVICE(&s->gem1), true, NULL);
if (nd->used) {
qemu_check_nic_model(nd, TYPE_CADENCE_GEM);
qdev_set_nic_properties(DEVICE(&s->gem0), nd);
}
nd = &nd_table[1];
if (nd->used) {
qemu_check_nic_model(nd, TYPE_CADENCE_GEM);
qdev_set_nic_properties(DEVICE(&s->gem1), nd);
}
object_property_set_int(OBJECT(&s->gem0), "revision", GEM_REVISION, errp); object_property_set_int(OBJECT(&s->gem0), "revision", GEM_REVISION, errp);
object_property_set_int(OBJECT(&s->gem0), "phy-addr", 8, errp); object_property_set_int(OBJECT(&s->gem0), "phy-addr", 8, errp);

7
hw/riscv/sifive_u.c
View File

@ -789,7 +789,6 @@ static void sifive_u_soc_realize(DeviceState *dev, Error **errp)
MemoryRegion *l2lim_mem = g_new(MemoryRegion, 1); MemoryRegion *l2lim_mem = g_new(MemoryRegion, 1);
char *plic_hart_config; char *plic_hart_config;
int i, j; int i, j;
NICInfo *nd = &nd_table[0];
qdev_prop_set_uint32(DEVICE(&s->u_cpus), "num-harts", ms->smp.cpus - 1); qdev_prop_set_uint32(DEVICE(&s->u_cpus), "num-harts", ms->smp.cpus - 1);
qdev_prop_set_uint32(DEVICE(&s->u_cpus), "hartid-base", 1); qdev_prop_set_uint32(DEVICE(&s->u_cpus), "hartid-base", 1);
@ -893,11 +892,7 @@ static void sifive_u_soc_realize(DeviceState *dev, Error **errp)
} }
sysbus_mmio_map(SYS_BUS_DEVICE(&s->otp), 0, memmap[SIFIVE_U_DEV_OTP].base); sysbus_mmio_map(SYS_BUS_DEVICE(&s->otp), 0, memmap[SIFIVE_U_DEV_OTP].base);
/* FIXME use qdev NIC properties instead of nd_table[] */ qemu_configure_nic_device(DEVICE(&s->gem), true, NULL);
if (nd->used) {
qemu_check_nic_model(nd, TYPE_CADENCE_GEM);
qdev_set_nic_properties(DEVICE(&s->gem), nd);
}
object_property_set_int(OBJECT(&s->gem), "revision", GEM_REVISION, object_property_set_int(OBJECT(&s->gem), "revision", GEM_REVISION,
&error_abort); &error_abort);
if (!sysbus_realize(SYS_BUS_DEVICE(&s->gem), errp)) { if (!sysbus_realize(SYS_BUS_DEVICE(&s->gem), errp)) {