pull-loongarch-20230106
-----BEGIN PGP SIGNATURE----- iLMEAAEIAB0WIQS4/x2g0v3LLaCcbCxAov/yOSY+3wUCY7e94gAKCRBAov/yOSY+ 3+YwA/9JAerEGzZIJfV2+QK4LWONOfIt7Ns5TR93gTjd+9rTsahgSIHRa2XHQLWZ TwY2eyTf8M+qiVOKa1wTCEfvr/iQwRuJBmsyQ/igdKgylEi9t6GEIG1NeGUxGkkR sCBJMtcqB4OKIX6PlyRiOm9kJxnNgQuiQ6ZB7uqIcVuYC/wxzA== =KsDP -----END PGP SIGNATURE----- Merge tag 'pull-loongarch-20230106' of https://gitlab.com/gaosong/qemu into staging pull-loongarch-20230106 # gpg: Signature made Fri 06 Jan 2023 06:21:22 GMT # gpg: using RSA key B8FF1DA0D2FDCB2DA09C6C2C40A2FFF239263EDF # gpg: Good signature from "Song Gao <m17746591750@163.com>" [unknown] # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: B8FF 1DA0 D2FD CB2D A09C 6C2C 40A2 FFF2 3926 3EDF * tag 'pull-loongarch-20230106' of https://gitlab.com/gaosong/qemu: hw/intc/loongarch_pch: Change default irq number of pch irq controller hw/intc/loongarch_pch_pic: add irq number property hw/intc/loongarch_pch_msi: add irq number property Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
commit
0ab12aa324
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@ -32,7 +32,7 @@ static void loongarch_msi_mem_write(void *opaque, hwaddr addr,
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*/
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irq_num = (val & 0xff) - s->irq_base;
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trace_loongarch_msi_set_irq(irq_num);
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assert(irq_num < PCH_MSI_IRQ_NUM);
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assert(irq_num < s->irq_num);
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qemu_set_irq(s->pch_msi_irq[irq_num], 1);
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}
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@ -49,6 +49,28 @@ static void pch_msi_irq_handler(void *opaque, int irq, int level)
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qemu_set_irq(s->pch_msi_irq[irq], level);
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}
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static void loongarch_pch_msi_realize(DeviceState *dev, Error **errp)
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{
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LoongArchPCHMSI *s = LOONGARCH_PCH_MSI(dev);
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if (!s->irq_num || s->irq_num > PCH_MSI_IRQ_NUM) {
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error_setg(errp, "Invalid 'msi_irq_num'");
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return;
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}
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s->pch_msi_irq = g_new(qemu_irq, s->irq_num);
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qdev_init_gpio_out(dev, s->pch_msi_irq, s->irq_num);
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qdev_init_gpio_in(dev, pch_msi_irq_handler, s->irq_num);
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}
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static void loongarch_pch_msi_unrealize(DeviceState *dev)
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{
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LoongArchPCHMSI *s = LOONGARCH_PCH_MSI(dev);
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g_free(s->pch_msi_irq);
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}
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static void loongarch_pch_msi_init(Object *obj)
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{
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LoongArchPCHMSI *s = LOONGARCH_PCH_MSI(obj);
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@ -59,12 +81,11 @@ static void loongarch_pch_msi_init(Object *obj)
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sysbus_init_mmio(sbd, &s->msi_mmio);
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msi_nonbroken = true;
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qdev_init_gpio_out(DEVICE(obj), s->pch_msi_irq, PCH_MSI_IRQ_NUM);
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qdev_init_gpio_in(DEVICE(obj), pch_msi_irq_handler, PCH_MSI_IRQ_NUM);
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}
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static Property loongarch_msi_properties[] = {
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DEFINE_PROP_UINT32("msi_irq_base", LoongArchPCHMSI, irq_base, 0),
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DEFINE_PROP_UINT32("msi_irq_num", LoongArchPCHMSI, irq_num, 0),
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DEFINE_PROP_END_OF_LIST(),
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};
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@ -72,6 +93,8 @@ static void loongarch_pch_msi_class_init(ObjectClass *klass, void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(klass);
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dc->realize = loongarch_pch_msi_realize;
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dc->unrealize = loongarch_pch_msi_unrealize;
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device_class_set_props(dc, loongarch_msi_properties);
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}
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@ -6,12 +6,16 @@
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*/
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#include "qemu/osdep.h"
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#include "qemu/bitops.h"
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#include "hw/sysbus.h"
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#include "hw/loongarch/virt.h"
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#include "hw/pci-host/ls7a.h"
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#include "hw/irq.h"
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#include "hw/intc/loongarch_pch_pic.h"
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#include "hw/qdev-properties.h"
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#include "migration/vmstate.h"
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#include "trace.h"
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#include "qapi/error.h"
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static void pch_pic_update_irq(LoongArchPCHPIC *s, uint64_t mask, int level)
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{
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@ -40,7 +44,7 @@ static void pch_pic_irq_handler(void *opaque, int irq, int level)
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LoongArchPCHPIC *s = LOONGARCH_PCH_PIC(opaque);
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uint64_t mask = 1ULL << irq;
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assert(irq < PCH_PIC_IRQ_NUM);
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assert(irq < s->irq_num);
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trace_loongarch_pch_pic_irq_handler(irq, level);
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if (s->intedge & mask) {
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@ -78,7 +82,12 @@ static uint64_t loongarch_pch_pic_low_readw(void *opaque, hwaddr addr,
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val = PCH_PIC_INT_ID_VAL;
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break;
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case PCH_PIC_INT_ID_HI:
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val = PCH_PIC_INT_ID_NUM;
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/*
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* With 7A1000 manual
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* bit 0-15 pch irqchip version
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* bit 16-31 irq number supported with pch irqchip
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*/
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val = deposit32(PCH_PIC_INT_ID_VER, 16, 16, s->irq_num - 1);
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break;
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case PCH_PIC_INT_MASK_LO:
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val = (uint32_t)s->int_mask;
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@ -365,6 +374,19 @@ static void loongarch_pch_pic_reset(DeviceState *d)
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s->int_polarity = 0x0;
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}
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static void loongarch_pch_pic_realize(DeviceState *dev, Error **errp)
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{
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LoongArchPCHPIC *s = LOONGARCH_PCH_PIC(dev);
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if (!s->irq_num || s->irq_num > VIRT_PCH_PIC_IRQ_NUM) {
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error_setg(errp, "Invalid 'pic_irq_num'");
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return;
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}
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qdev_init_gpio_out(dev, s->parent_irq, s->irq_num);
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qdev_init_gpio_in(dev, pch_pic_irq_handler, s->irq_num);
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}
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static void loongarch_pch_pic_init(Object *obj)
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{
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LoongArchPCHPIC *s = LOONGARCH_PCH_PIC(obj);
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@ -382,10 +404,13 @@ static void loongarch_pch_pic_init(Object *obj)
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sysbus_init_mmio(sbd, &s->iomem8);
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sysbus_init_mmio(sbd, &s->iomem32_high);
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qdev_init_gpio_out(DEVICE(obj), s->parent_irq, PCH_PIC_IRQ_NUM);
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qdev_init_gpio_in(DEVICE(obj), pch_pic_irq_handler, PCH_PIC_IRQ_NUM);
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}
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static Property loongarch_pch_pic_properties[] = {
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DEFINE_PROP_UINT32("pch_pic_irq_num", LoongArchPCHPIC, irq_num, 0),
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DEFINE_PROP_END_OF_LIST(),
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};
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static const VMStateDescription vmstate_loongarch_pch_pic = {
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.name = TYPE_LOONGARCH_PCH_PIC,
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.version_id = 1,
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@ -411,8 +436,10 @@ static void loongarch_pch_pic_class_init(ObjectClass *klass, void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(klass);
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dc->realize = loongarch_pch_pic_realize;
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dc->reset = loongarch_pch_pic_reset;
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dc->vmsd = &vmstate_loongarch_pch_pic;
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device_class_set_props(dc, loongarch_pch_pic_properties);
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}
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static const TypeInfo loongarch_pch_pic_info = {
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@ -553,7 +553,7 @@ static void loongarch_irq_init(LoongArchMachineState *lams)
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LoongArchCPU *lacpu;
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CPULoongArchState *env;
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CPUState *cpu_state;
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int cpu, pin, i;
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int cpu, pin, i, start, num;
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ipi = qdev_new(TYPE_LOONGARCH_IPI);
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sysbus_realize_and_unref(SYS_BUS_DEVICE(ipi), &error_fatal);
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@ -616,6 +616,8 @@ static void loongarch_irq_init(LoongArchMachineState *lams)
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}
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pch_pic = qdev_new(TYPE_LOONGARCH_PCH_PIC);
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num = VIRT_PCH_PIC_IRQ_NUM;
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qdev_prop_set_uint32(pch_pic, "pch_pic_irq_num", num);
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d = SYS_BUS_DEVICE(pch_pic);
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sysbus_realize_and_unref(d, &error_fatal);
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memory_region_add_subregion(get_system_memory(), VIRT_IOAPIC_REG_BASE,
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@ -627,20 +629,23 @@ static void loongarch_irq_init(LoongArchMachineState *lams)
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VIRT_IOAPIC_REG_BASE + PCH_PIC_INT_STATUS_LO,
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sysbus_mmio_get_region(d, 2));
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/* Connect 64 pch_pic irqs to extioi */
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for (int i = 0; i < PCH_PIC_IRQ_NUM; i++) {
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/* Connect pch_pic irqs to extioi */
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for (int i = 0; i < num; i++) {
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qdev_connect_gpio_out(DEVICE(d), i, qdev_get_gpio_in(extioi, i));
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}
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pch_msi = qdev_new(TYPE_LOONGARCH_PCH_MSI);
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qdev_prop_set_uint32(pch_msi, "msi_irq_base", PCH_MSI_IRQ_START);
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start = num;
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num = EXTIOI_IRQS - start;
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qdev_prop_set_uint32(pch_msi, "msi_irq_base", start);
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qdev_prop_set_uint32(pch_msi, "msi_irq_num", num);
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d = SYS_BUS_DEVICE(pch_msi);
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sysbus_realize_and_unref(d, &error_fatal);
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sysbus_mmio_map(d, 0, VIRT_PCH_MSI_ADDR_LOW);
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for (i = 0; i < PCH_MSI_IRQ_NUM; i++) {
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/* Connect 192 pch_msi irqs to extioi */
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for (i = 0; i < num; i++) {
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/* Connect pch_msi irqs to extioi */
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qdev_connect_gpio_out(DEVICE(d), i,
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qdev_get_gpio_in(extioi, i + PCH_MSI_IRQ_START));
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qdev_get_gpio_in(extioi, i + start));
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}
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loongarch_devices_init(pch_pic, lams);
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@ -8,15 +8,16 @@
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#define TYPE_LOONGARCH_PCH_MSI "loongarch_pch_msi"
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OBJECT_DECLARE_SIMPLE_TYPE(LoongArchPCHMSI, LOONGARCH_PCH_MSI)
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/* Msi irq start start from 64 to 255 */
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#define PCH_MSI_IRQ_START 64
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/* MSI irq start from 32 to 255 */
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#define PCH_MSI_IRQ_START 32
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#define PCH_MSI_IRQ_END 255
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#define PCH_MSI_IRQ_NUM 192
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#define PCH_MSI_IRQ_NUM 224
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struct LoongArchPCHMSI {
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SysBusDevice parent_obj;
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qemu_irq pch_msi_irq[PCH_MSI_IRQ_NUM];
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qemu_irq *pch_msi_irq;
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MemoryRegion msi_mmio;
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/* irq base passed to upper extioi intc */
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unsigned int irq_base;
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unsigned int irq_num;
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};
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@ -9,11 +9,8 @@
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#define PCH_PIC_NAME(name) TYPE_LOONGARCH_PCH_PIC#name
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OBJECT_DECLARE_SIMPLE_TYPE(LoongArchPCHPIC, LOONGARCH_PCH_PIC)
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#define PCH_PIC_IRQ_START 0
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#define PCH_PIC_IRQ_END 63
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#define PCH_PIC_IRQ_NUM 64
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#define PCH_PIC_INT_ID_VAL 0x7000000UL
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#define PCH_PIC_INT_ID_NUM 0x3f0001UL
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#define PCH_PIC_INT_ID_VER 0x1UL
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#define PCH_PIC_INT_ID_LO 0x00
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#define PCH_PIC_INT_ID_HI 0x04
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@ -66,4 +63,5 @@ struct LoongArchPCHPIC {
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MemoryRegion iomem32_low;
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MemoryRegion iomem32_high;
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MemoryRegion iomem8;
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unsigned int irq_num;
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};
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@ -32,9 +32,9 @@
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* 0 ~ 16 irqs used for non-pci device while 16 ~ 64 irqs
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* used for pci device.
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*/
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#define VIRT_PCH_PIC_IRQ_NUM 32
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#define PCH_PIC_IRQ_OFFSET 64
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#define VIRT_DEVICE_IRQS 16
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#define VIRT_PCI_IRQS 48
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#define VIRT_UART_IRQ (PCH_PIC_IRQ_OFFSET + 2)
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#define VIRT_UART_BASE 0x1fe001e0
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#define VIRT_UART_SIZE 0X100
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