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x86 queue, 2018-08-16

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Bug fix:
 * Some guests may crash when using "-cpu host" due to TOPOEXT,
   disable it by default
 
 Features:
 * PV_SEND_IPI feature bit
 * Icelake-{Server,Client} CPU models
 * New CPUID feature bits: PV_SEND_IPI, WBNOINVD, PCONFIG, ARCH_CAPABILITIES
 
 Documentation:
 * docs/qemu-cpu-models.texi
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Merge remote-tracking branch 'remotes/ehabkost/tags/x86-next-pull-request' into staging

x86 queue, 2018-08-16

Bug fix:
* Some guests may crash when using "-cpu host" due to TOPOEXT,
  disable it by default

Features:
* PV_SEND_IPI feature bit
* Icelake-{Server,Client} CPU models
* New CPUID feature bits: PV_SEND_IPI, WBNOINVD, PCONFIG, ARCH_CAPABILITIES

Documentation:
* docs/qemu-cpu-models.texi

# gpg: Signature made Fri 17 Aug 2018 02:33:09 BST
# gpg:                using RSA key 2807936F984DC5A6
# gpg: Good signature from "Eduardo Habkost <ehabkost@redhat.com>"
# Primary key fingerprint: 5A32 2FD5 ABC4 D3DB ACCF  D1AA 2807 936F 984D C5A6

* remotes/ehabkost/tags/x86-next-pull-request:
  i386: Disable TOPOEXT by default on "-cpu host"
  target-i386: adds PV_SEND_IPI CPUID feature bit
  i386: Add new CPU model Icelake-{Server,Client}
  i386: Add CPUID bit for WBNOINVD
  i386: Add CPUID bit for PCONFIG
  i386: Add CPUID bit and feature words for IA32_ARCH_CAPABILITIES MSR
  i386: Add new MSR indices for IA32_PRED_CMD and IA32_ARCH_CAPABILITIES
  docs: add guidance on configuring CPU models for x86

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Peter Maydell 2018-08-17 09:46:00 +01:00
commit 0abaa41d93
6 changed files with 629 additions and 5 deletions
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1
MAINTAINERS
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@ -289,6 +289,7 @@ F: tests/tcg/i386/
F: tests/tcg/x86_64/
F: hw/i386/
F: disas/i386.c
F: docs/qemu-cpu-models.texi
T: git git://github.com/ehabkost/qemu.git x86-next
Xtensa

7
Makefile
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@ -357,6 +357,7 @@ DOCS=qemu-doc.html qemu-doc.txt qemu.1 qemu-img.1 qemu-nbd.8 qemu-ga.8
DOCS+=docs/interop/qemu-qmp-ref.html docs/interop/qemu-qmp-ref.txt docs/interop/qemu-qmp-ref.7
DOCS+=docs/interop/qemu-ga-ref.html docs/interop/qemu-ga-ref.txt docs/interop/qemu-ga-ref.7
DOCS+=docs/qemu-block-drivers.7
DOCS+=docs/qemu-cpu-models.7
ifdef CONFIG_VIRTFS
DOCS+=fsdev/virtfs-proxy-helper.1
endif
@ -778,6 +779,7 @@ distclean: clean
rm -f docs/interop/qemu-qmp-ref.pdf docs/interop/qemu-ga-ref.pdf
rm -f docs/interop/qemu-qmp-ref.html docs/interop/qemu-ga-ref.html
rm -f docs/qemu-block-drivers.7
rm -f docs/qemu-cpu-models.7
for d in $(TARGET_DIRS); do \
rm -rf $$d || exit 1 ; \
done
@ -823,6 +825,7 @@ ifdef CONFIG_POSIX
$(INSTALL_DIR) "$(DESTDIR)$(mandir)/man7"
$(INSTALL_DATA) docs/interop/qemu-qmp-ref.7 "$(DESTDIR)$(mandir)/man7"
$(INSTALL_DATA) docs/qemu-block-drivers.7 "$(DESTDIR)$(mandir)/man7"
$(INSTALL_DATA) docs/qemu-cpu-models.7 "$(DESTDIR)$(mandir)/man7"
ifneq ($(TOOLS),)
$(INSTALL_DATA) qemu-img.1 "$(DESTDIR)$(mandir)/man1"
$(INSTALL_DIR) "$(DESTDIR)$(mandir)/man8"
@ -965,6 +968,7 @@ fsdev/virtfs-proxy-helper.1: fsdev/virtfs-proxy-helper.texi
qemu-nbd.8: qemu-nbd.texi qemu-option-trace.texi
qemu-ga.8: qemu-ga.texi
docs/qemu-block-drivers.7: docs/qemu-block-drivers.texi
docs/qemu-cpu-models.7: docs/qemu-cpu-models.texi
html: qemu-doc.html docs/interop/qemu-qmp-ref.html docs/interop/qemu-ga-ref.html
info: qemu-doc.info docs/interop/qemu-qmp-ref.info docs/interop/qemu-ga-ref.info
@ -974,7 +978,8 @@ txt: qemu-doc.txt docs/interop/qemu-qmp-ref.txt docs/interop/qemu-ga-ref.txt
qemu-doc.html qemu-doc.info qemu-doc.pdf qemu-doc.txt: \
qemu-img.texi qemu-nbd.texi qemu-options.texi qemu-option-trace.texi \
qemu-monitor.texi qemu-img-cmds.texi qemu-ga.texi \
qemu-monitor-info.texi docs/qemu-block-drivers.texi
qemu-monitor-info.texi docs/qemu-block-drivers.texi \
docs/qemu-cpu-models.texi
docs/interop/qemu-ga-ref.dvi docs/interop/qemu-ga-ref.html \
docs/interop/qemu-ga-ref.info docs/interop/qemu-ga-ref.pdf \

484
docs/qemu-cpu-models.texi Normal file
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@ -0,0 +1,484 @@
@c man begin SYNOPSIS
QEMU / KVM CPU model configuration
@c man end
@c man begin DESCRIPTION
@menu
* recommendations_cpu_models_x86:: Recommendations for KVM CPU model configuration on x86 hosts
* cpu_model_syntax_apps:: Syntax for configuring CPU models
@end menu
QEMU / KVM virtualization supports two ways to configure CPU models
@table @option
@item Host passthrough
This passes the host CPU model features, model, stepping, exactly to the
guest. Note that KVM may filter out some host CPU model features if they
cannot be supported with virtualization. Live migration is unsafe when
this mode is used as libvirt / QEMU cannot guarantee a stable CPU is
exposed to the guest across hosts. This is the recommended CPU to use,
provided live migration is not required.
@item Named model
QEMU comes with a number of predefined named CPU models, that typically
refer to specific generations of hardware released by Intel and AMD.
These allow the guest VMs to have a degree of isolation from the host CPU,
allowing greater flexibility in live migrating between hosts with differing
hardware.
@end table
In both cases, it is possible to optionally add or remove individual CPU
features, to alter what is presented to the guest by default.
Libvirt supports a third way to configure CPU models known as "Host model".
This uses the QEMU "Named model" feature, automatically picking a CPU model
that is similar the host CPU, and then adding extra features to approximate
the host model as closely as possible. This does not guarantee the CPU family,
stepping, etc will precisely match the host CPU, as they would with "Host
passthrough", but gives much of the benefit of passthrough, while making
live migration safe.
@node recommendations_cpu_models_x86
@subsection Recommendations for KVM CPU model configuration on x86 hosts
The information that follows provides recommendations for configuring
CPU models on x86 hosts. The goals are to maximise performance, while
protecting guest OS against various CPU hardware flaws, and optionally
enabling live migration between hosts with hetergeneous CPU models.
@menu
* preferred_cpu_models_intel_x86:: Preferred CPU models for Intel x86 hosts
* important_cpu_features_intel_x86:: Important CPU features for Intel x86 hosts
* preferred_cpu_models_amd_x86:: Preferred CPU models for AMD x86 hosts
* important_cpu_features_amd_x86:: Important CPU features for AMD x86 hosts
* default_cpu_models_x86:: Default x86 CPU models
* other_non_recommended_cpu_models_x86:: Other non-recommended x86 CPUs
@end menu
@node preferred_cpu_models_intel_x86
@subsubsection Preferred CPU models for Intel x86 hosts
The following CPU models are preferred for use on Intel hosts. Administrators /
applications are recommended to use the CPU model that matches the generation
of the host CPUs in use. In a deployment with a mixture of host CPU models
between machines, if live migration compatibility is required, use the newest
CPU model that is compatible across all desired hosts.
@table @option
@item @code{Skylake-Server}
@item @code{Skylake-Server-IBRS}
Intel Xeon Processor (Skylake, 2016)
@item @code{Skylake-Client}
@item @code{Skylake-Client-IBRS}
Intel Core Processor (Skylake, 2015)
@item @code{Broadwell}
@item @code{Broadwell-IBRS}
@item @code{Broadwell-noTSX}
@item @code{Broadwell-noTSX-IBRS}
Intel Core Processor (Broadwell, 2014)
@item @code{Haswell}
@item @code{Haswell-IBRS}
@item @code{Haswell-noTSX}
@item @code{Haswell-noTSX-IBRS}
Intel Core Processor (Haswell, 2013)
@item @code{IvyBridge}
@item @code{IvyBridge-IBRS}
Intel Xeon E3-12xx v2 (Ivy Bridge, 2012)
@item @code{SandyBridge}
@item @code{SandyBridge-IBRS}
Intel Xeon E312xx (Sandy Bridge, 2011)
@item @code{Westmere}
@item @code{Westmere-IBRS}
Westmere E56xx/L56xx/X56xx (Nehalem-C, 2010)
@item @code{Nehalem}
@item @code{Nehalem-IBRS}
Intel Core i7 9xx (Nehalem Class Core i7, 2008)
@item @code{Penryn}
Intel Core 2 Duo P9xxx (Penryn Class Core 2, 2007)
@item @code{Conroe}
Intel Celeron_4x0 (Conroe/Merom Class Core 2, 2006)
@end table
@node important_cpu_features_intel_x86
@subsubsection Important CPU features for Intel x86 hosts
The following are important CPU features that should be used on Intel x86
hosts, when available in the host CPU. Some of them require explicit
configuration to enable, as they are not included by default in some, or all,
of the named CPU models listed above. In general all of these features are
included if using "Host passthrough" or "Host model".
@table @option
@item @code{pcid}
Recommended to mitigate the cost of the Meltdown (CVE-2017-5754) fix
Included by default in Haswell, Broadwell & Skylake Intel CPU models.
Should be explicitly turned on for Westmere, SandyBridge, and IvyBridge
Intel CPU models. Note that some desktop/mobile Westmere CPUs cannot
support this feature.
@item @code{spec-ctrl}
Required to enable the Spectre (CVE-2017-5753 and CVE-2017-5715) fix,
in cases where retpolines are not sufficient.
Included by default in Intel CPU models with -IBRS suffix.
Must be explicitly turned on for Intel CPU models without -IBRS suffix.
Requires the host CPU microcode to support this feature before it
can be used for guest CPUs.
@item @code{ssbd}
Required to enable the CVE-2018-3639 fix
Not included by default in any Intel CPU model.
Must be explicitly turned on for all Intel CPU models.
Requires the host CPU microcode to support this feature before it
can be used for guest CPUs.
@item @code{pdpe1gb}
Recommended to allow guest OS to use 1GB size pages
Not included by default in any Intel CPU model.
Should be explicitly turned on for all Intel CPU models.
Note that not all CPU hardware will support this feature.
@end table
@node preferred_cpu_models_amd_x86
@subsubsection Preferred CPU models for AMD x86 hosts
The following CPU models are preferred for use on Intel hosts. Administrators /
applications are recommended to use the CPU model that matches the generation
of the host CPUs in use. In a deployment with a mixture of host CPU models
between machines, if live migration compatibility is required, use the newest
CPU model that is compatible across all desired hosts.
@table @option
@item @code{EPYC}
@item @code{EPYC-IBPB}
AMD EPYC Processor (2017)
@item @code{Opteron_G5}
AMD Opteron 63xx class CPU (2012)
@item @code{Opteron_G4}
AMD Opteron 62xx class CPU (2011)
@item @code{Opteron_G3}
AMD Opteron 23xx (Gen 3 Class Opteron, 2009)
@item @code{Opteron_G2}
AMD Opteron 22xx (Gen 2 Class Opteron, 2006)
@item @code{Opteron_G1}
AMD Opteron 240 (Gen 1 Class Opteron, 2004)
@end table
@node important_cpu_features_amd_x86
@subsubsection Important CPU features for AMD x86 hosts
The following are important CPU features that should be used on AMD x86
hosts, when available in the host CPU. Some of them require explicit
configuration to enable, as they are not included by default in some, or all,
of the named CPU models listed above. In general all of these features are
included if using "Host passthrough" or "Host model".
@table @option
@item @code{ibpb}
Required to enable the Spectre (CVE-2017-5753 and CVE-2017-5715) fix,
in cases where retpolines are not sufficient.
Included by default in AMD CPU models with -IBPB suffix.
Must be explicitly turned on for AMD CPU models without -IBPB suffix.
Requires the host CPU microcode to support this feature before it
can be used for guest CPUs.
@item @code{virt-ssbd}
Required to enable the CVE-2018-3639 fix
Not included by default in any AMD CPU model.
Must be explicitly turned on for all AMD CPU models.
This should be provided to guests, even if amd-ssbd is also
provided, for maximum guest compatibility.
Note for some QEMU / libvirt versions, this must be force enabled
when when using "Host model", because this is a virtual feature
that doesn't exist in the physical host CPUs.
@item @code{amd-ssbd}
Required to enable the CVE-2018-3639 fix
Not included by default in any AMD CPU model.
Must be explicitly turned on for all AMD CPU models.
This provides higher performance than virt-ssbd so should be
exposed to guests whenever available in the host. virt-ssbd
should none the less also be exposed for maximum guest
compatability as some kernels only know about virt-ssbd.
@item @code{amd-no-ssb}
Recommended to indicate the host is not vulnerable CVE-2018-3639
Not included by default in any AMD CPU model.
Future hardware genarations of CPU will not be vulnerable to
CVE-2018-3639, and thus the guest should be told not to enable
its mitigations, by exposing amd-no-ssb. This is mutually
exclusive with virt-ssbd and amd-ssbd.
@item @code{pdpe1gb}
Recommended to allow guest OS to use 1GB size pages
Not included by default in any AMD CPU model.
Should be explicitly turned on for all AMD CPU models.
Note that not all CPU hardware will support this feature.
@end table
@node default_cpu_models_x86
@subsubsection Default x86 CPU models
The default QEMU CPU models are designed such that they can run on all hosts.
If an application does not wish to do perform any host compatibility checks
before launching guests, the default is guaranteed to work.
The default CPU models will, however, leave the guest OS vulnerable to various
CPU hardware flaws, so their use is strongly discouraged. Applications should
follow the earlier guidance to setup a better CPU configuration, with host
passthrough recommended if live migration is not needed.
@table @option
@item @code{qemu32}
@item @code{qemu64}
QEMU Virtual CPU version 2.5+ (32 & 64 bit variants)
qemu64 is used for x86_64 guests and qemu32 is used for i686 guests, when no
-cpu argument is given to QEMU, or no <cpu> is provided in libvirt XML.
@end table
@node other_non_recommended_cpu_models_x86
@subsubsection Other non-recommended x86 CPUs
The following CPUs models are compatible with most AMD and Intel x86 hosts, but
their usage is discouraged, as they expose a very limited featureset, which
prevents guests having optimal performance.
@table @option
@item @code{kvm32}
@item @code{kvm64}
Common KVM processor (32 & 64 bit variants)
Legacy models just for historical compatibility with ancient QEMU versions.
@item @code{486}
@item @code{athlon}
@item @code{phenom}
@item @code{coreduo}
@item @code{core2duo}
@item @code{n270}
@item @code{pentium}
@item @code{pentium2}
@item @code{pentium3}
Various very old x86 CPU models, mostly predating the introduction of
hardware assisted virtualization, that should thus not be required for
running virtual machines.
@end table
@node cpu_model_syntax_apps
@subsection Syntax for configuring CPU models
The example below illustrate the approach to configuring the various
CPU models / features in QEMU and libvirt
@menu
* cpu_model_syntax_qemu:: QEMU command line
* cpu_model_syntax_libvirt:: Libvirt guest XML
@end menu
@node cpu_model_syntax_qemu
@subsubsection QEMU command line
@table @option
@item Host passthrough
@example
$ qemu-system-x86_64 -cpu host
@end example
With feature customization:
@example
$ qemu-system-x86_64 -cpu host,-vmx,...
@end example
@item Named CPU models
@example
$ qemu-system-x86_64 -cpu Westmere
@end example
With feature customization:
@example
$ qemu-system-x86_64 -cpu Westmere,+pcid,...
@end example
@end table
@node cpu_model_syntax_libvirt
@subsubsection Libvirt guest XML
@table @option
@item Host passthrough
@example
<cpu mode='host-passthrough'/>
@end example
With feature customization:
@example
<cpu mode='host-passthrough'>
<feature name="vmx" policy="disable"/>
...
</cpu>
@end example
@item Host model
@example
<cpu mode='host-model'/>
@end example
With feature customization:
@example
<cpu mode='host-model'>
<feature name="vmx" policy="disable"/>
...
</cpu>
@end example
@item Named model
@example
<cpu mode='custom'>
<model name="Westmere"/>
</cpu>
@end example
With feature customization:
@example
<cpu mode='custom'>
<model name="Westmere"/>
<feature name="pcid" policy="require"/>
...
</cpu>
@end example
@end table
@c man end
@ignore
@setfilename qemu-cpu-models
@settitle QEMU / KVM CPU model configuration
@c man begin SEEALSO
The HTML documentation of QEMU for more precise information and Linux
user mode emulator invocation.
@c man end
@c man begin AUTHOR
Daniel P. Berrange
@c man end
@end ignore

6
qemu-doc.texi
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@ -135,6 +135,7 @@ accelerator is required to use more than one host CPU for emulation.
* pcsys_keys:: Keys in the graphical frontends
* mux_keys:: Keys in the character backend multiplexer
* pcsys_monitor:: QEMU Monitor
* cpu_models:: CPU models
* disk_images:: Disk Images
* pcsys_network:: Network emulation
* pcsys_other_devs:: Other Devices
@ -602,6 +603,11 @@ The monitor understands integers expressions for every integer
argument. You can use register names to get the value of specifics
CPU registers by prefixing them with @emph{$}.
@node cpu_models
@section CPU models
@include docs/qemu-cpu-models.texi
@node disk_images
@section Disk Images

130
target/i386/cpu.c
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@ -849,6 +849,12 @@ static FeatureWordInfo feature_word_info[FEATURE_WORDS] = {
},
.cpuid_eax = 0x80000001, .cpuid_reg = R_ECX,
.tcg_features = TCG_EXT3_FEATURES,
/*
* TOPOEXT is always allowed but can't be enabled blindly by
* "-cpu host", as it requires consistent cache topology info
* to be provided so it doesn't confuse guests.
*/
.no_autoenable_flags = CPUID_EXT3_TOPOEXT,
},
[FEAT_C000_0001_EDX] = {
.feat_names = {
@ -868,7 +874,7 @@ static FeatureWordInfo feature_word_info[FEATURE_WORDS] = {
.feat_names = {
"kvmclock", "kvm-nopiodelay", "kvm-mmu", "kvmclock",
"kvm-asyncpf", "kvm-steal-time", "kvm-pv-eoi", "kvm-pv-unhalt",
NULL, "kvm-pv-tlb-flush", NULL, NULL,
NULL, "kvm-pv-tlb-flush", NULL, "kvm-pv-ipi",
NULL, NULL, NULL, NULL,
NULL, NULL, NULL, NULL,
NULL, NULL, NULL, NULL,
@ -997,15 +1003,16 @@ static FeatureWordInfo feature_word_info[FEATURE_WORDS] = {
NULL, NULL, NULL, NULL,
NULL, NULL, NULL, NULL,
NULL, NULL, NULL, NULL,
NULL, NULL, NULL, NULL,
NULL, NULL, "pconfig", NULL,
NULL, NULL, NULL, NULL,
NULL, NULL, "spec-ctrl", NULL,
NULL, NULL, NULL, "ssbd",
NULL, "arch-capabilities", NULL, "ssbd",
},
.cpuid_eax = 7,
.cpuid_needs_ecx = true, .cpuid_ecx = 0,
.cpuid_reg = R_EDX,
.tcg_features = TCG_7_0_EDX_FEATURES,
.unmigratable_flags = CPUID_7_0_EDX_ARCH_CAPABILITIES,
},
[FEAT_8000_0007_EDX] = {
.feat_names = {
@ -1027,7 +1034,7 @@ static FeatureWordInfo feature_word_info[FEATURE_WORDS] = {
.feat_names = {
NULL, NULL, NULL, NULL,
NULL, NULL, NULL, NULL,
NULL, NULL, NULL, NULL,
NULL, "wbnoinvd", NULL, NULL,
"ibpb", NULL, NULL, NULL,
NULL, NULL, NULL, NULL,
NULL, NULL, NULL, NULL,
@ -2379,6 +2386,121 @@ static X86CPUDefinition builtin_x86_defs[] = {
.xlevel = 0x80000008,
.model_id = "Intel Xeon Processor (Skylake, IBRS)",
},
{
.name = "Icelake-Client",
.level = 0xd,
.vendor = CPUID_VENDOR_INTEL,
.family = 6,
.model = 126,
.stepping = 0,
.features[FEAT_1_EDX] =
CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
CPUID_DE | CPUID_FP87,
.features[FEAT_1_ECX] =
CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
.features[FEAT_8000_0001_EDX] =
CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
CPUID_EXT2_SYSCALL,
.features[FEAT_8000_0001_ECX] =
CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
.features[FEAT_8000_0008_EBX] =
CPUID_8000_0008_EBX_WBNOINVD,
.features[FEAT_7_0_EBX] =
CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX |
CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_MPX | CPUID_7_0_EBX_INTEL_PT,
.features[FEAT_7_0_ECX] =
CPUID_7_0_ECX_VBMI | CPUID_7_0_ECX_UMIP | CPUID_7_0_ECX_PKU |
CPUID_7_0_ECX_OSPKE | CPUID_7_0_ECX_VBMI2 | CPUID_7_0_ECX_GFNI |
CPUID_7_0_ECX_VAES | CPUID_7_0_ECX_VPCLMULQDQ |
CPUID_7_0_ECX_AVX512VNNI | CPUID_7_0_ECX_AVX512BITALG |
CPUID_7_0_ECX_AVX512_VPOPCNTDQ,
.features[FEAT_7_0_EDX] =
CPUID_7_0_EDX_SPEC_CTRL | CPUID_7_0_EDX_SPEC_CTRL_SSBD,
/* Missing: XSAVES (not supported by some Linux versions,
* including v4.1 to v4.12).
* KVM doesn't yet expose any XSAVES state save component,
* and the only one defined in Skylake (processor tracing)
* probably will block migration anyway.
*/
.features[FEAT_XSAVE] =
CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC |
CPUID_XSAVE_XGETBV1,
.features[FEAT_6_EAX] =
CPUID_6_EAX_ARAT,
.xlevel = 0x80000008,
.model_id = "Intel Core Processor (Icelake)",
},
{
.name = "Icelake-Server",
.level = 0xd,
.vendor = CPUID_VENDOR_INTEL,
.family = 6,
.model = 134,
.stepping = 0,
.features[FEAT_1_EDX] =
CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
CPUID_DE | CPUID_FP87,
.features[FEAT_1_ECX] =
CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
.features[FEAT_8000_0001_EDX] =
CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP |
CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
.features[FEAT_8000_0001_ECX] =
CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
.features[FEAT_8000_0008_EBX] =
CPUID_8000_0008_EBX_WBNOINVD,
.features[FEAT_7_0_EBX] =
CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX |
CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_MPX | CPUID_7_0_EBX_CLWB |
CPUID_7_0_EBX_AVX512F | CPUID_7_0_EBX_AVX512DQ |
CPUID_7_0_EBX_AVX512BW | CPUID_7_0_EBX_AVX512CD |
CPUID_7_0_EBX_AVX512VL | CPUID_7_0_EBX_CLFLUSHOPT |
CPUID_7_0_EBX_INTEL_PT,
.features[FEAT_7_0_ECX] =
CPUID_7_0_ECX_VBMI | CPUID_7_0_ECX_UMIP | CPUID_7_0_ECX_PKU |
CPUID_7_0_ECX_OSPKE | CPUID_7_0_ECX_VBMI2 | CPUID_7_0_ECX_GFNI |
CPUID_7_0_ECX_VAES | CPUID_7_0_ECX_VPCLMULQDQ |
CPUID_7_0_ECX_AVX512VNNI | CPUID_7_0_ECX_AVX512BITALG |
CPUID_7_0_ECX_AVX512_VPOPCNTDQ | CPUID_7_0_ECX_LA57,
.features[FEAT_7_0_EDX] =
CPUID_7_0_EDX_PCONFIG | CPUID_7_0_EDX_SPEC_CTRL |
CPUID_7_0_EDX_SPEC_CTRL_SSBD,
/* Missing: XSAVES (not supported by some Linux versions,
* including v4.1 to v4.12).
* KVM doesn't yet expose any XSAVES state save component,
* and the only one defined in Skylake (processor tracing)
* probably will block migration anyway.
*/
.features[FEAT_XSAVE] =
CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC |
CPUID_XSAVE_XGETBV1,
.features[FEAT_6_EAX] =
CPUID_6_EAX_ARAT,
.xlevel = 0x80000008,
.model_id = "Intel Xeon Processor (Icelake)",
},
{
.name = "KnightsMill",
.level = 0xd,

6
target/i386/cpu.h
View File

@ -354,6 +354,8 @@ typedef enum X86Seg {
#define MSR_TSC_ADJUST 0x0000003b
#define MSR_IA32_SPEC_CTRL 0x48
#define MSR_VIRT_SSBD 0xc001011f
#define MSR_IA32_PRED_CMD 0x49
#define MSR_IA32_ARCH_CAPABILITIES 0x10a
#define MSR_IA32_TSCDEADLINE 0x6e0
#define FEATURE_CONTROL_LOCKED (1<<0)
@ -687,9 +689,13 @@ typedef uint32_t FeatureWordArray[FEATURE_WORDS];
#define CPUID_7_0_EDX_AVX512_4VNNIW (1U << 2) /* AVX512 Neural Network Instructions */
#define CPUID_7_0_EDX_AVX512_4FMAPS (1U << 3) /* AVX512 Multiply Accumulation Single Precision */
#define CPUID_7_0_EDX_PCONFIG (1U << 18) /* Platform Configuration */
#define CPUID_7_0_EDX_SPEC_CTRL (1U << 26) /* Speculation Control */
#define CPUID_7_0_EDX_ARCH_CAPABILITIES (1U << 29) /*Arch Capabilities*/
#define CPUID_7_0_EDX_SPEC_CTRL_SSBD (1U << 31) /* Speculative Store Bypass Disable */
#define CPUID_8000_0008_EBX_WBNOINVD (1U << 9) /* Write back and
do not invalidate cache */
#define CPUID_8000_0008_EBX_IBPB (1U << 12) /* Indirect Branch Prediction Barrier */
#define CPUID_XSAVE_XSAVEOPT (1U << 0)