PCI interrupt support - PCI BIOS interrupt remapping - more accurate memory mapping - 'info pci' monitor command
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@823 c046a42c-6fe2-441c-8c8c-71466251a162
This commit is contained in:
bellard
parent
4a9c9687c6
commit
0ac32c8375
543
hw/pci.c
543
hw/pci.c
@ -25,6 +25,21 @@
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//#define DEBUG_PCI
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#define PCI_VENDOR_ID 0x00 /* 16 bits */
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#define PCI_DEVICE_ID 0x02 /* 16 bits */
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#define PCI_COMMAND 0x04 /* 16 bits */
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#define PCI_COMMAND_IO 0x1 /* Enable response in I/O space */
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#define PCI_COMMAND_MEMORY 0x2 /* Enable response in Memory space */
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#define PCI_CLASS_DEVICE 0x0a /* Device class */
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#define PCI_INTERRUPT_LINE 0x3c /* 8 bits */
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#define PCI_INTERRUPT_PIN 0x3d /* 8 bits */
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#define PCI_MIN_GNT 0x3e /* 8 bits */
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#define PCI_MAX_LAT 0x3f /* 8 bits */
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/* just used for simpler irq handling. */
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#define PCI_DEVICES_MAX 64
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#define PCI_IRQ_WORDS ((PCI_DEVICES_MAX + 31) / 32)
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typedef struct PCIBridge {
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uint32_t config_reg;
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PCIDevice **pci_bus[256];
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@ -32,6 +47,8 @@ typedef struct PCIBridge {
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static PCIBridge pci_bridge;
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target_phys_addr_t pci_mem_base;
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static int pci_irq_index;
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static uint32_t pci_irq_levels[4][PCI_IRQ_WORDS];
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/* -1 for devfn means auto assign */
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PCIDevice *pci_register_device(const char *name, int instance_size,
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@ -42,6 +59,9 @@ PCIDevice *pci_register_device(const char *name, int instance_size,
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PCIBridge *s = &pci_bridge;
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PCIDevice *pci_dev, **bus;
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if (pci_irq_index >= PCI_DEVICES_MAX)
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return NULL;
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if (!s->pci_bus[bus_num]) {
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s->pci_bus[bus_num] = qemu_mallocz(256 * sizeof(PCIDevice *));
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if (!s->pci_bus[bus_num])
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@ -62,8 +82,14 @@ PCIDevice *pci_register_device(const char *name, int instance_size,
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pci_dev->bus_num = bus_num;
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pci_dev->devfn = devfn;
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pstrcpy(pci_dev->name, sizeof(pci_dev->name), name);
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if (!config_read)
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config_read = pci_default_read_config;
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if (!config_write)
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config_write = pci_default_write_config;
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pci_dev->config_read = config_read;
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pci_dev->config_write = config_write;
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pci_dev->irq_index = pci_irq_index++;
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bus[devfn] = pci_dev;
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return pci_dev;
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}
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@ -83,30 +109,160 @@ void pci_register_io_region(PCIDevice *pci_dev, int region_num,
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r->map_func = map_func;
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}
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static void pci_config_writel(void* opaque, uint32_t addr, uint32_t val)
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static void pci_addr_writel(void* opaque, uint32_t addr, uint32_t val)
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{
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PCIBridge *s = opaque;
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s->config_reg = val;
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}
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static uint32_t pci_config_readl(void* opaque, uint32_t addr)
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static uint32_t pci_addr_readl(void* opaque, uint32_t addr)
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{
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PCIBridge *s = opaque;
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return s->config_reg;
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}
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static void unmap_region(PCIIORegion *r)
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static void pci_update_mappings(PCIDevice *d)
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{
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if (r->addr == -1)
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PCIIORegion *r;
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int cmd, i;
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uint32_t last_addr, new_addr;
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cmd = le16_to_cpu(*(uint16_t *)(d->config + PCI_COMMAND));
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for(i = 0; i < 6; i++) {
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r = &d->io_regions[i];
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if (r->size != 0) {
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if (r->type & PCI_ADDRESS_SPACE_IO) {
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if (cmd & PCI_COMMAND_IO) {
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new_addr = le32_to_cpu(*(uint32_t *)(d->config +
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0x10 + i * 4));
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new_addr = new_addr & ~(r->size - 1);
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last_addr = new_addr + r->size - 1;
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/* NOTE: we have only 64K ioports on PC */
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if (last_addr <= new_addr || new_addr == 0 ||
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last_addr >= 0x10000) {
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new_addr = -1;
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}
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} else {
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new_addr = -1;
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}
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} else {
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if (cmd & PCI_COMMAND_MEMORY) {
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new_addr = le32_to_cpu(*(uint32_t *)(d->config +
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0x10 + i * 4));
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new_addr = new_addr & ~(r->size - 1);
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last_addr = new_addr + r->size - 1;
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/* NOTE: we do not support wrapping */
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/* XXX: as we cannot support really dynamic
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mappings, we handle specific values as invalid
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mappings. */
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if (last_addr <= new_addr || new_addr == 0 ||
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last_addr == -1) {
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new_addr = -1;
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}
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} else {
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new_addr = -1;
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}
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}
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/* now do the real mapping */
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if (new_addr != r->addr) {
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if (r->addr != -1) {
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if (r->type & PCI_ADDRESS_SPACE_IO) {
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int class;
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/* NOTE: specific hack for IDE in PC case:
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only one byte must be mapped. */
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class = d->config[0x0a] | (d->config[0x0b] << 8);
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if (class == 0x0101 && r->size == 4) {
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isa_unassign_ioport(r->addr + 2, 1);
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} else {
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isa_unassign_ioport(r->addr, r->size);
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}
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} else {
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cpu_register_physical_memory(r->addr + pci_mem_base,
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r->size,
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IO_MEM_UNASSIGNED);
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}
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}
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r->addr = new_addr;
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if (r->addr != -1) {
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r->map_func(d, i, r->addr, r->size, r->type);
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}
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}
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}
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}
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}
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uint32_t pci_default_read_config(PCIDevice *d,
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uint32_t address, int len)
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{
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uint32_t val;
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switch(len) {
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case 1:
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val = d->config[address];
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break;
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case 2:
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val = le16_to_cpu(*(uint16_t *)(d->config + address));
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break;
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default:
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case 4:
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val = le32_to_cpu(*(uint32_t *)(d->config + address));
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break;
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}
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return val;
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}
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void pci_default_write_config(PCIDevice *d,
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uint32_t address, uint32_t val, int len)
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{
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int can_write, i;
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uint32_t end;
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if (len == 4 && (address >= 0x10 && address < 0x10 + 4 * 6)) {
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PCIIORegion *r;
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int reg;
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reg = (address - 0x10) >> 2;
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r = &d->io_regions[reg];
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if (r->size == 0)
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goto default_config;
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/* compute the stored value */
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val &= ~(r->size - 1);
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val |= r->type;
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*(uint32_t *)(d->config + 0x10 + reg * 4) = cpu_to_le32(val);
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pci_update_mappings(d);
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return;
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#ifdef DEBUG_PCI
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printf("unmap addr=%08x size=%08x\n", r->addr, r->size);
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#endif
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if (r->type & PCI_ADDRESS_SPACE_IO) {
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isa_unassign_ioport(r->addr, r->size);
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} else {
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cpu_register_physical_memory(r->addr + pci_mem_base, r->size,
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IO_MEM_UNASSIGNED);
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}
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default_config:
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/* not efficient, but simple */
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for(i = 0; i < len; i++) {
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/* default read/write accesses */
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switch(address) {
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case 0x00:
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case 0x01:
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case 0x02:
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case 0x03:
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case 0x08:
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case 0x09:
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case 0x0a:
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case 0x0b:
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case 0x0e:
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case 0x3d:
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can_write = 0;
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break;
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default:
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can_write = 1;
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break;
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}
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if (can_write) {
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d->config[address] = val;
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}
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address++;
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val >>= 8;
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}
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end = address + len;
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if (end > PCI_COMMAND && address < (PCI_COMMAND + 2)) {
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/* if the command register is modified, we must modify the mappings */
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pci_update_mappings(d);
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}
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}
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@ -115,7 +271,7 @@ static void pci_data_write(void *opaque, uint32_t addr,
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{
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PCIBridge *s = opaque;
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PCIDevice **bus, *pci_dev;
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int config_addr, reg;
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int config_addr;
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#if defined(DEBUG_PCI) && 0
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printf("pci_data_write: addr=%08x val=%08x len=%d\n",
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@ -134,41 +290,11 @@ static void pci_data_write(void *opaque, uint32_t addr,
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if (!pci_dev)
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return;
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config_addr = (s->config_reg & 0xfc) | (addr & 3);
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#if defined(DEBUG_PCI)
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printf("pci_config_write: %s: addr=%02x val=%08x len=%d\n",
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pci_dev->name, config_addr, val, len);
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#endif
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if (len == 4 && (config_addr >= 0x10 && config_addr < 0x10 + 4 * 6)) {
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PCIIORegion *r;
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reg = (config_addr - 0x10) >> 2;
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r = &pci_dev->io_regions[reg];
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if (r->size == 0)
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goto default_config;
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if (val != 0xffffffff && val != 0) {
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/* XXX: the memory assignment should be global to handle
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overlaps, but it is not needed at this stage */
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/* first unmap the old region */
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unmap_region(r);
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/* change the address */
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if (r->type & PCI_ADDRESS_SPACE_IO)
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r->addr = val & ~0x3;
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else
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r->addr = val & ~0xf;
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#ifdef DEBUG_PCI
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printf("map addr=%08x size=%08x type=%d\n",
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r->addr, r->size, r->type);
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#endif
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r->map_func(pci_dev, reg, r->addr, r->size, r->type);
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}
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/* now compute the stored value */
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val &= ~(r->size - 1);
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val |= r->type;
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*(uint32_t *)(pci_dev->config + 0x10 + reg * 4) = cpu_to_le32(val);
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} else {
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default_config:
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pci_dev->config_write(pci_dev, config_addr, val, len);
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}
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pci_dev->config_write(pci_dev, config_addr, val, len);
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}
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static uint32_t pci_data_read(void *opaque, uint32_t addr,
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@ -238,28 +364,13 @@ static uint32_t pci_data_readl(void* opaque, uint32_t addr)
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/* i440FX PCI bridge */
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static uint32_t i440_read_config(PCIDevice *d,
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uint32_t address, int len)
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{
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uint32_t val;
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val = 0;
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memcpy(&val, d->config + address, len);
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return val;
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}
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static void i440_write_config(PCIDevice *d,
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uint32_t address, uint32_t val, int len)
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{
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memcpy(d->config + address, &val, len);
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}
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void i440fx_init(void)
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{
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PCIBridge *s = &pci_bridge;
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PCIDevice *d;
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register_ioport_write(0xcf8, 4, 4, pci_config_writel, s);
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register_ioport_read(0xcf8, 4, 4, pci_config_readl, s);
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register_ioport_write(0xcf8, 4, 4, pci_addr_writel, s);
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register_ioport_read(0xcf8, 4, 4, pci_addr_readl, s);
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register_ioport_write(0xcfc, 4, 1, pci_data_writeb, s);
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register_ioport_write(0xcfc, 4, 2, pci_data_writew, s);
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@ -269,7 +380,7 @@ void i440fx_init(void)
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register_ioport_read(0xcfc, 4, 4, pci_data_readl, s);
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d = pci_register_device("i440FX", sizeof(PCIDevice), 0, 0,
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i440_read_config, i440_write_config);
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NULL, NULL);
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d->config[0x00] = 0x86; // vendor_id
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d->config[0x01] = 0x80;
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@ -282,35 +393,295 @@ void i440fx_init(void)
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d->config[0x0e] = 0x01; // header_type
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}
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/* NOTE: the following should be done by the BIOS */
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/* PIIX3 PCI to ISA bridge */
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typedef struct PIIX3State {
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PCIDevice dev;
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} PIIX3State;
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PIIX3State *piix3_state;
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static void piix3_reset(PIIX3State *d)
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{
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uint8_t *pci_conf = d->dev.config;
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pci_conf[0x04] = 0x07; // master, memory and I/O
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pci_conf[0x05] = 0x00;
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pci_conf[0x06] = 0x00;
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pci_conf[0x07] = 0x02; // PCI_status_devsel_medium
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pci_conf[0x4c] = 0x4d;
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pci_conf[0x4e] = 0x03;
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pci_conf[0x4f] = 0x00;
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pci_conf[0x60] = 0x80;
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pci_conf[0x69] = 0x02;
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pci_conf[0x70] = 0x80;
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pci_conf[0x76] = 0x0c;
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pci_conf[0x77] = 0x0c;
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pci_conf[0x78] = 0x02;
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pci_conf[0x79] = 0x00;
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pci_conf[0x80] = 0x00;
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pci_conf[0x82] = 0x00;
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pci_conf[0xa0] = 0x08;
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pci_conf[0xa0] = 0x08;
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pci_conf[0xa2] = 0x00;
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pci_conf[0xa3] = 0x00;
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pci_conf[0xa4] = 0x00;
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pci_conf[0xa5] = 0x00;
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pci_conf[0xa6] = 0x00;
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pci_conf[0xa7] = 0x00;
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pci_conf[0xa8] = 0x0f;
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pci_conf[0xaa] = 0x00;
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pci_conf[0xab] = 0x00;
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pci_conf[0xac] = 0x00;
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pci_conf[0xae] = 0x00;
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}
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void piix3_init(void)
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{
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PIIX3State *d;
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uint8_t *pci_conf;
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d = (PIIX3State *)pci_register_device("PIIX3", sizeof(PIIX3State),
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0, -1,
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NULL, NULL);
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piix3_state = d;
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pci_conf = d->dev.config;
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pci_conf[0x00] = 0x86; // Intel
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pci_conf[0x01] = 0x80;
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pci_conf[0x02] = 0x00; // 82371SB PIIX3 PCI-to-ISA bridge (Step A1)
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pci_conf[0x03] = 0x70;
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pci_conf[0x0a] = 0x01; // class_sub = PCI_ISA
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pci_conf[0x0b] = 0x06; // class_base = PCI_bridge
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pci_conf[0x0e] = 0x80; // header_type = PCI_multifunction, generic
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piix3_reset(d);
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}
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/***********************************************************/
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/* generic PCI irq support */
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/* return the global irq number corresponding to a given device irq
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pin. We could also use the bus number to have a more precise
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mapping. */
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static inline int pci_slot_get_pirq(PCIDevice *pci_dev, int irq_num)
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{
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int slot_addend;
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slot_addend = (pci_dev->devfn >> 3);
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return (irq_num + slot_addend) & 3;
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}
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/* 0 <= irq_num <= 3. level must be 0 or 1 */
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void pci_set_irq(PCIDevice *pci_dev, int irq_num, int level)
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{
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int irq_index, shift, pic_irq, pic_level;
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uint32_t *p;
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irq_num = pci_slot_get_pirq(pci_dev, irq_num);
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irq_index = pci_dev->irq_index;
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p = &pci_irq_levels[irq_num][irq_index >> 5];
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shift = (irq_index & 0x1f);
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*p = (*p & ~(1 << shift)) | (level << shift);
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/* now we change the pic irq level according to the piix irq mappings */
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pic_irq = piix3_state->dev.config[0x60 + irq_num];
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if (pic_irq < 16) {
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/* the pic level is the logical OR of all the PCI irqs mapped
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to it */
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pic_level = 0;
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#if (PCI_IRQ_WORDS == 2)
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pic_level = ((pci_irq_levels[irq_num][0] |
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pci_irq_levels[irq_num][1]) != 0);
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#else
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{
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int i;
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pic_level = 0;
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for(i = 0; i < PCI_IRQ_WORDS; i++) {
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if (pci_irq_levels[irq_num][i]) {
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pic_level = 1;
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break;
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}
|
||||
}
|
||||
}
|
||||
#endif
|
||||
pic_set_irq(pic_irq, pic_level);
|
||||
}
|
||||
}
|
||||
|
||||
/***********************************************************/
|
||||
/* monitor info on PCI */
|
||||
|
||||
static void pci_info_device(PCIDevice *d)
|
||||
{
|
||||
int i, class;
|
||||
PCIIORegion *r;
|
||||
|
||||
printf(" Bus %2d, device %3d, function %d:\n",
|
||||
d->bus_num, d->devfn >> 3, d->devfn & 7);
|
||||
class = le16_to_cpu(*((uint16_t *)(d->config + PCI_CLASS_DEVICE)));
|
||||
printf(" ");
|
||||
switch(class) {
|
||||
case 0x0101:
|
||||
printf("IDE controller");
|
||||
break;
|
||||
case 0x0200:
|
||||
printf("Ethernet controller");
|
||||
break;
|
||||
case 0x0300:
|
||||
printf("VGA controller");
|
||||
break;
|
||||
default:
|
||||
printf("Class %04x", class);
|
||||
break;
|
||||
}
|
||||
printf(": PCI device %04x:%04x\n",
|
||||
le16_to_cpu(*((uint16_t *)(d->config + PCI_VENDOR_ID))),
|
||||
le16_to_cpu(*((uint16_t *)(d->config + PCI_DEVICE_ID))));
|
||||
|
||||
if (d->config[PCI_INTERRUPT_PIN] != 0) {
|
||||
printf(" IRQ %d.\n", d->config[PCI_INTERRUPT_LINE]);
|
||||
}
|
||||
for(i = 0;i < 6; i++) {
|
||||
r = &d->io_regions[i];
|
||||
if (r->size != 0) {
|
||||
printf(" BAR%d: ", i);
|
||||
if (r->type & PCI_ADDRESS_SPACE_IO) {
|
||||
printf("I/O at 0x%04x [0x%04x].\n",
|
||||
r->addr, r->addr + r->size - 1);
|
||||
} else {
|
||||
printf("32 bit memory at 0x%08x [0x%08x].\n",
|
||||
r->addr, r->addr + r->size - 1);
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
void pci_info(void)
|
||||
{
|
||||
PCIBridge *s = &pci_bridge;
|
||||
PCIDevice **bus;
|
||||
int bus_num, devfn;
|
||||
|
||||
for(bus_num = 0; bus_num < 256; bus_num++) {
|
||||
bus = s->pci_bus[bus_num];
|
||||
if (bus) {
|
||||
for(devfn = 0; devfn < 256; devfn++) {
|
||||
if (bus[devfn])
|
||||
pci_info_device(bus[devfn]);
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/***********************************************************/
|
||||
/* XXX: the following should be moved to the PC BIOS */
|
||||
|
||||
static uint32_t isa_inb(uint32_t addr)
|
||||
{
|
||||
return cpu_inb(cpu_single_env, addr);
|
||||
}
|
||||
|
||||
static void isa_outb(uint32_t val, uint32_t addr)
|
||||
{
|
||||
cpu_outb(cpu_single_env, addr, val);
|
||||
}
|
||||
|
||||
static uint32_t isa_inw(uint32_t addr)
|
||||
{
|
||||
return cpu_inw(cpu_single_env, addr);
|
||||
}
|
||||
|
||||
static void isa_outw(uint32_t val, uint32_t addr)
|
||||
{
|
||||
cpu_outw(cpu_single_env, addr, val);
|
||||
}
|
||||
|
||||
static uint32_t isa_inl(uint32_t addr)
|
||||
{
|
||||
return cpu_inl(cpu_single_env, addr);
|
||||
}
|
||||
|
||||
static void isa_outl(uint32_t val, uint32_t addr)
|
||||
{
|
||||
cpu_outl(cpu_single_env, addr, val);
|
||||
}
|
||||
|
||||
static void pci_config_writel(PCIDevice *d, uint32_t addr, uint32_t val)
|
||||
{
|
||||
PCIBridge *s = &pci_bridge;
|
||||
s->config_reg = 0x80000000 | (d->bus_num << 16) |
|
||||
(d->devfn << 8) | addr;
|
||||
pci_data_write(s, 0, val, 4);
|
||||
}
|
||||
|
||||
static void pci_config_writew(PCIDevice *d, uint32_t addr, uint32_t val)
|
||||
{
|
||||
PCIBridge *s = &pci_bridge;
|
||||
s->config_reg = 0x80000000 | (d->bus_num << 16) |
|
||||
(d->devfn << 8) | (addr & ~3);
|
||||
pci_data_write(s, addr & 3, val, 2);
|
||||
}
|
||||
|
||||
static void pci_config_writeb(PCIDevice *d, uint32_t addr, uint32_t val)
|
||||
{
|
||||
PCIBridge *s = &pci_bridge;
|
||||
s->config_reg = 0x80000000 | (d->bus_num << 16) |
|
||||
(d->devfn << 8) | (addr & ~3);
|
||||
pci_data_write(s, addr & 3, val, 1);
|
||||
}
|
||||
|
||||
static uint32_t pci_config_readl(PCIDevice *d, uint32_t addr)
|
||||
{
|
||||
PCIBridge *s = &pci_bridge;
|
||||
s->config_reg = 0x80000000 | (d->bus_num << 16) |
|
||||
(d->devfn << 8) | addr;
|
||||
return pci_data_read(s, 0, 4);
|
||||
}
|
||||
|
||||
static uint32_t pci_config_readw(PCIDevice *d, uint32_t addr)
|
||||
{
|
||||
PCIBridge *s = &pci_bridge;
|
||||
s->config_reg = 0x80000000 | (d->bus_num << 16) |
|
||||
(d->devfn << 8) | (addr & ~3);
|
||||
return pci_data_read(s, addr & 3, 2);
|
||||
}
|
||||
|
||||
static uint32_t pci_config_readb(PCIDevice *d, uint32_t addr)
|
||||
{
|
||||
PCIBridge *s = &pci_bridge;
|
||||
s->config_reg = 0x80000000 | (d->bus_num << 16) |
|
||||
(d->devfn << 8) | (addr & ~3);
|
||||
return pci_data_read(s, addr & 3, 1);
|
||||
}
|
||||
|
||||
static uint32_t pci_bios_io_addr;
|
||||
static uint32_t pci_bios_mem_addr;
|
||||
/* host irqs corresponding to PCI irqs A-D */
|
||||
static uint8_t pci_irqs[4] = { 11, 9, 11, 9 };
|
||||
|
||||
static void pci_set_io_region_addr(PCIDevice *d, int region_num, uint32_t addr)
|
||||
{
|
||||
PCIBridge *s = &pci_bridge;
|
||||
PCIIORegion *r;
|
||||
uint16_t cmd;
|
||||
|
||||
s->config_reg = 0x80000000 | (d->bus_num << 16) |
|
||||
(d->devfn << 8) | (0x10 + region_num * 4);
|
||||
pci_data_write(s, 0, addr, 4);
|
||||
pci_config_writel(d, 0x10 + region_num * 4, addr);
|
||||
r = &d->io_regions[region_num];
|
||||
|
||||
/* enable memory mappings */
|
||||
cmd = pci_config_readw(d, PCI_COMMAND);
|
||||
if (r->type & PCI_ADDRESS_SPACE_IO)
|
||||
d->config[0x04] |= 1;
|
||||
cmd |= 1;
|
||||
else
|
||||
d->config[0x04] |= 2;
|
||||
cmd |= 2;
|
||||
pci_config_writew(d, PCI_COMMAND, cmd);
|
||||
}
|
||||
|
||||
|
||||
static void pci_bios_init_device(PCIDevice *d)
|
||||
{
|
||||
int class;
|
||||
PCIIORegion *r;
|
||||
uint32_t *paddr;
|
||||
int i;
|
||||
int i, pin, pic_irq;
|
||||
|
||||
class = d->config[0x0a] | (d->config[0x0b] << 8);
|
||||
switch(class) {
|
||||
@ -321,6 +692,10 @@ static void pci_bios_init_device(PCIDevice *d)
|
||||
pci_set_io_region_addr(d, 2, 0x170);
|
||||
pci_set_io_region_addr(d, 3, 0x374);
|
||||
break;
|
||||
case 0x0300:
|
||||
/* VGA: map frame buffer to default Bochs VBE address */
|
||||
pci_set_io_region_addr(d, 0, 0xE0000000);
|
||||
break;
|
||||
default:
|
||||
/* default memory mappings */
|
||||
for(i = 0; i < 6; i++) {
|
||||
@ -337,6 +712,14 @@ static void pci_bios_init_device(PCIDevice *d)
|
||||
}
|
||||
break;
|
||||
}
|
||||
|
||||
/* map the interrupt */
|
||||
pin = pci_config_readb(d, PCI_INTERRUPT_PIN);
|
||||
if (pin != 0) {
|
||||
pin = pci_slot_get_pirq(d, pin - 1);
|
||||
pic_irq = pci_irqs[pin];
|
||||
pci_config_writeb(d, PCI_INTERRUPT_LINE, pic_irq);
|
||||
}
|
||||
}
|
||||
|
||||
/*
|
||||
@ -348,11 +731,25 @@ void pci_bios_init(void)
|
||||
{
|
||||
PCIBridge *s = &pci_bridge;
|
||||
PCIDevice **bus;
|
||||
int bus_num, devfn;
|
||||
int bus_num, devfn, i, irq;
|
||||
uint8_t elcr[2];
|
||||
|
||||
pci_bios_io_addr = 0xc000;
|
||||
pci_bios_mem_addr = 0xf0000000;
|
||||
|
||||
/* activate IRQ mappings */
|
||||
elcr[0] = 0x00;
|
||||
elcr[1] = 0x00;
|
||||
for(i = 0; i < 4; i++) {
|
||||
irq = pci_irqs[i];
|
||||
/* set to trigger level */
|
||||
elcr[irq >> 3] |= (1 << (irq & 7));
|
||||
/* activate irq remapping in PIIX */
|
||||
pci_config_writeb((PCIDevice *)piix3_state, 0x60 + i, irq);
|
||||
}
|
||||
isa_outb(elcr[0], 0x4d0);
|
||||
isa_outb(elcr[1], 0x4d1);
|
||||
|
||||
for(bus_num = 0; bus_num < 256; bus_num++) {
|
||||
bus = s->pci_bus[bus_num];
|
||||
if (bus) {
|
||||
@ -363,5 +760,3 @@ void pci_bios_init(void)
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
|
||||
Loading…
Reference in New Issue
Block a user