target/riscv: Add *envcfg.HADE related check in address translation
When menvcfg.HADE is 1, hardware updating of PTE A/D bits is enabled during single-stage address translation. When the hypervisor extension is implemented, if menvcfg.HADE is 1, hardware updating of PTE A/D bits is enabled during G-stage address translation. Set *envcfg.HADE default true for backward compatibility. Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn> Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn> Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Message-ID: <20230224040852.37109-6-liweiwei@iscas.ac.cn> Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
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@ -613,8 +613,10 @@ static void riscv_cpu_reset_hold(Object *obj)
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env->bins = 0;
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env->two_stage_lookup = false;
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env->menvcfg = (cpu->cfg.ext_svpbmt ? MENVCFG_PBMTE : 0);
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env->henvcfg = (cpu->cfg.ext_svpbmt ? HENVCFG_PBMTE : 0);
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env->menvcfg = (cpu->cfg.ext_svpbmt ? MENVCFG_PBMTE : 0) |
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(cpu->cfg.ext_svadu ? MENVCFG_HADE : 0);
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env->henvcfg = (cpu->cfg.ext_svpbmt ? HENVCFG_PBMTE : 0) |
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(cpu->cfg.ext_svadu ? HENVCFG_HADE : 0);
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/* Initialized default priorities of local interrupts. */
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for (i = 0; i < ARRAY_SIZE(env->miprio); i++) {
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@ -937,9 +937,11 @@ restart:
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}
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bool pbmte = env->menvcfg & MENVCFG_PBMTE;
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bool hade = env->menvcfg & MENVCFG_HADE;
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if (first_stage && two_stage && riscv_cpu_virt_enabled(env)) {
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pbmte = pbmte && (env->henvcfg & HENVCFG_PBMTE);
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hade = hade && (env->henvcfg & HENVCFG_HADE);
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}
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if (riscv_cpu_sxl(env) == MXL_RV32) {
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@ -998,6 +1000,10 @@ restart:
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/* Page table updates need to be atomic with MTTCG enabled */
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if (updated_pte != pte) {
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if (!hade) {
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return TRANSLATE_FAIL;
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}
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/*
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* - if accessed or dirty bits need updating, and the PTE is
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* in RAM, then we do so atomically with a compare and swap.
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