target/arm: Add Neoverse-N1 registers
Add implementation defined registers for neoverse-n1 which would be accessed by TF-A. Since there is no DSU in Qemu, CPUCFR_EL1.SCU bit is set to 1 to avoid DSU registers definition. Signed-off-by: Chen Baozi <chenbaozi@phytium.com.cn> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Tested-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org> Message-id: 20230313033936.585669-1-chenbaozi@phytium.com.cn Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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@ -21,6 +21,7 @@
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#include "qemu/osdep.h"
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#include "qapi/error.h"
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#include "cpu.h"
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#include "cpregs.h"
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#include "qemu/module.h"
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#include "sysemu/kvm.h"
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#include "sysemu/hvf.h"
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@ -1027,6 +1028,72 @@ static void aarch64_a64fx_initfn(Object *obj)
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/* TODO: Add A64FX specific HPC extension registers */
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}
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static const ARMCPRegInfo neoverse_n1_cp_reginfo[] = {
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{ .name = "ATCR_EL1", .state = ARM_CP_STATE_AA64,
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.opc0 = 3, .opc1 = 0, .crn = 15, .crm = 7, .opc2 = 0,
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.access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
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{ .name = "ATCR_EL2", .state = ARM_CP_STATE_AA64,
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.opc0 = 3, .opc1 = 4, .crn = 15, .crm = 7, .opc2 = 0,
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.access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
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{ .name = "ATCR_EL3", .state = ARM_CP_STATE_AA64,
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.opc0 = 3, .opc1 = 6, .crn = 15, .crm = 7, .opc2 = 0,
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.access = PL3_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
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{ .name = "ATCR_EL12", .state = ARM_CP_STATE_AA64,
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.opc0 = 3, .opc1 = 5, .crn = 15, .crm = 7, .opc2 = 0,
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.access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
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{ .name = "AVTCR_EL2", .state = ARM_CP_STATE_AA64,
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.opc0 = 3, .opc1 = 4, .crn = 15, .crm = 7, .opc2 = 1,
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.access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
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{ .name = "CPUACTLR_EL1", .state = ARM_CP_STATE_AA64,
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.opc0 = 3, .opc1 = 0, .crn = 15, .crm = 1, .opc2 = 0,
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.access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
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{ .name = "CPUACTLR2_EL1", .state = ARM_CP_STATE_AA64,
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.opc0 = 3, .opc1 = 0, .crn = 15, .crm = 1, .opc2 = 1,
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.access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
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{ .name = "CPUACTLR3_EL1", .state = ARM_CP_STATE_AA64,
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.opc0 = 3, .opc1 = 0, .crn = 15, .crm = 1, .opc2 = 2,
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.access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
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/*
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* Report CPUCFR_EL1.SCU as 1, as we do not implement the DSU
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* (and in particular its system registers).
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*/
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{ .name = "CPUCFR_EL1", .state = ARM_CP_STATE_AA64,
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.opc0 = 3, .opc1 = 0, .crn = 15, .crm = 0, .opc2 = 0,
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.access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 4 },
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{ .name = "CPUECTLR_EL1", .state = ARM_CP_STATE_AA64,
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.opc0 = 3, .opc1 = 0, .crn = 15, .crm = 1, .opc2 = 4,
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.access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0x961563010 },
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{ .name = "CPUPCR_EL3", .state = ARM_CP_STATE_AA64,
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.opc0 = 3, .opc1 = 6, .crn = 15, .crm = 8, .opc2 = 1,
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.access = PL3_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
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{ .name = "CPUPMR_EL3", .state = ARM_CP_STATE_AA64,
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.opc0 = 3, .opc1 = 6, .crn = 15, .crm = 8, .opc2 = 3,
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.access = PL3_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
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{ .name = "CPUPOR_EL3", .state = ARM_CP_STATE_AA64,
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.opc0 = 3, .opc1 = 6, .crn = 15, .crm = 8, .opc2 = 2,
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.access = PL3_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
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{ .name = "CPUPSELR_EL3", .state = ARM_CP_STATE_AA64,
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.opc0 = 3, .opc1 = 6, .crn = 15, .crm = 8, .opc2 = 0,
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.access = PL3_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
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{ .name = "CPUPWRCTLR_EL1", .state = ARM_CP_STATE_AA64,
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.opc0 = 3, .opc1 = 0, .crn = 15, .crm = 2, .opc2 = 7,
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.access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
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{ .name = "ERXPFGCDN_EL1", .state = ARM_CP_STATE_AA64,
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.opc0 = 3, .opc1 = 0, .crn = 15, .crm = 2, .opc2 = 2,
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.access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
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{ .name = "ERXPFGCTL_EL1", .state = ARM_CP_STATE_AA64,
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.opc0 = 3, .opc1 = 0, .crn = 15, .crm = 2, .opc2 = 1,
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.access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
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{ .name = "ERXPFGF_EL1", .state = ARM_CP_STATE_AA64,
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.opc0 = 3, .opc1 = 0, .crn = 15, .crm = 2, .opc2 = 0,
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.access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
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};
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static void define_neoverse_n1_cp_reginfo(ARMCPU *cpu)
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{
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define_arm_cp_regs(cpu, neoverse_n1_cp_reginfo);
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}
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static void aarch64_neoverse_n1_initfn(Object *obj)
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{
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ARMCPU *cpu = ARM_CPU(obj);
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@ -1094,6 +1161,8 @@ static void aarch64_neoverse_n1_initfn(Object *obj)
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/* From D5.1 AArch64 PMU register summary */
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cpu->isar.reset_pmcr_el0 = 0x410c3000;
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define_neoverse_n1_cp_reginfo(cpu);
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}
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static void aarch64_host_initfn(Object *obj)
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