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tcg/s390x: Support SELGR instruction in movcond

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The new select instruction provides two separate register inputs,
whereas the old load-on-condition instruction overlaps one of the
register inputs with the destination.

Reviewed-by: Ilya Leoshkevich <iii@linux.ibm.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
This commit is contained in:
Richard Henderson 2022-12-02 04:05:38 +00:00
parent 23d1394a6d
commit 0bbf0f7acf
1 changed files with 15 additions and 0 deletions
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15
tcg/s390x/tcg-target.c.inc
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@ -202,6 +202,8 @@ typedef enum S390Opcode {
RRFa_XRK = 0xb9f7, RRFa_XRK = 0xb9f7,
RRFa_XGRK = 0xb9e7, RRFa_XGRK = 0xb9e7,
RRFam_SELGR = 0xb9e3,
RRFc_LOCR = 0xb9f2, RRFc_LOCR = 0xb9f2,
RRFc_LOCGR = 0xb9e2, RRFc_LOCGR = 0xb9e2,
@ -626,12 +628,20 @@ static void tcg_out_insn_RRE(TCGContext *s, S390Opcode op,
tcg_out32(s, (op << 16) | (r1 << 4) | r2); tcg_out32(s, (op << 16) | (r1 << 4) | r2);
} }
/* RRF-a without the m4 field */
static void tcg_out_insn_RRFa(TCGContext *s, S390Opcode op, static void tcg_out_insn_RRFa(TCGContext *s, S390Opcode op,
TCGReg r1, TCGReg r2, TCGReg r3) TCGReg r1, TCGReg r2, TCGReg r3)
{ {
tcg_out32(s, (op << 16) | (r3 << 12) | (r1 << 4) | r2); tcg_out32(s, (op << 16) | (r3 << 12) | (r1 << 4) | r2);
} }
/* RRF-a with the m4 field */
static void tcg_out_insn_RRFam(TCGContext *s, S390Opcode op,
TCGReg r1, TCGReg r2, TCGReg r3, int m4)
{
tcg_out32(s, (op << 16) | (r3 << 12) | (m4 << 8) | (r1 << 4) | r2);
}
static void tcg_out_insn_RRFc(TCGContext *s, S390Opcode op, static void tcg_out_insn_RRFc(TCGContext *s, S390Opcode op,
TCGReg r1, TCGReg r2, int m3) TCGReg r1, TCGReg r2, int m3)
{ {
@ -1376,6 +1386,11 @@ static void tgen_movcond_int(TCGContext *s, TCGType type, TCGReg dest,
src = v4; src = v4;
} }
} else { } else {
if (HAVE_FACILITY(MISC_INSN_EXT3)) {
/* Emit: dest = cc ? v3 : v4. */
tcg_out_insn(s, RRFam, SELGR, dest, v3, v4, cc);
return;
}
if (dest == v4) { if (dest == v4) {
src = v3; src = v3;
} else { } else {