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tests/tcg: Add arm and aarch64 pc alignment tests

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Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Richard Henderson 2021-11-03 00:03:52 -04:00 committed by Peter Maydell
parent 8dc89f1faa
commit 0bdce4861f
4 changed files with 89 additions and 2 deletions
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4
tests/tcg/aarch64/Makefile.target
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@ -8,8 +8,8 @@ VPATH += $(ARM_SRC)
AARCH64_SRC=$(SRC_PATH)/tests/tcg/aarch64
VPATH += $(AARCH64_SRC)
# Float-convert Tests
AARCH64_TESTS=fcvt
# Base architecture tests
AARCH64_TESTS=fcvt pcalign-a64
fcvt: LDFLAGS+=-lm

37
tests/tcg/aarch64/pcalign-a64.c Normal file
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@ -0,0 +1,37 @@
/* Test PC misalignment exception */
#include <assert.h>
#include <signal.h>
#include <stdlib.h>
#include <stdio.h>
static void *expected;
static void sigbus(int sig, siginfo_t *info, void *vuc)
{
assert(info->si_code == BUS_ADRALN);
assert(info->si_addr == expected);
exit(EXIT_SUCCESS);
}
int main()
{
void *tmp;
struct sigaction sa = {
.sa_sigaction = sigbus,
.sa_flags = SA_SIGINFO
};
if (sigaction(SIGBUS, &sa, NULL) < 0) {
perror("sigaction");
return EXIT_FAILURE;
}
asm volatile("adr %0, 1f + 1\n\t"
"str %0, %1\n\t"
"br %0\n"
"1:"
: "=&r"(tmp), "=m"(expected));
abort();
}

4
tests/tcg/arm/Makefile.target
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@ -29,6 +29,10 @@ run-fcvt: fcvt
$(call run-test,fcvt,$(QEMU) $<,"$< on $(TARGET_NAME)")
$(call diff-out,fcvt,$(ARM_SRC)/fcvt.ref)
# PC alignment test
ARM_TESTS += pcalign-a32
pcalign-a32: CFLAGS+=-marm
ifeq ($(CONFIG_ARM_COMPATIBLE_SEMIHOSTING),y)
# Semihosting smoke test for linux-user

46
tests/tcg/arm/pcalign-a32.c Normal file
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@ -0,0 +1,46 @@
/* Test PC misalignment exception */
#ifdef __thumb__
#error "This test must be compiled for ARM"
#endif
#include <assert.h>
#include <signal.h>
#include <stdlib.h>
#include <stdio.h>
static void *expected;
static void sigbus(int sig, siginfo_t *info, void *vuc)
{
assert(info->si_code == BUS_ADRALN);
assert(info->si_addr == expected);
exit(EXIT_SUCCESS);
}
int main()
{
void *tmp;
struct sigaction sa = {
.sa_sigaction = sigbus,
.sa_flags = SA_SIGINFO
};
if (sigaction(SIGBUS, &sa, NULL) < 0) {
perror("sigaction");
return EXIT_FAILURE;
}
asm volatile("adr %0, 1f + 2\n\t"
"str %0, %1\n\t"
"bx %0\n"
"1:"
: "=&r"(tmp), "=m"(expected));
/*
* From v8, it is CONSTRAINED UNPREDICTABLE whether BXWritePC aligns
* the address or not. If so, we can legitimately fall through.
*/
return EXIT_SUCCESS;
}