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target/i386: enumerate bit 56 of MSR_IA32_VMX_BASIC

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On parts that enumerate IA32_VMX_BASIC MSR bit as 1, any exception vector
can be delivered with or without an error code if the other consistency
checks are satisfied.

Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
This commit is contained in:
Paolo Bonzini 2023-09-20 17:41:17 +02:00
parent 005ad32358
commit 0c49c9180c
3 changed files with 3 additions and 0 deletions
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1
scripts/kvm/vmxcap
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@ -115,6 +115,7 @@ controls = [
(50, 53): 'VMCS memory type', (50, 53): 'VMCS memory type',
54: 'INS/OUTS instruction information', 54: 'INS/OUTS instruction information',
55: 'IA32_VMX_TRUE_*_CTLS support', 55: 'IA32_VMX_TRUE_*_CTLS support',
56: 'Skip checks on event error code',
}, },
msr = MSR_IA32_VMX_BASIC, msr = MSR_IA32_VMX_BASIC,
), ),

1
target/i386/cpu.c
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@ -1340,6 +1340,7 @@ FeatureWordInfo feature_word_info[FEATURE_WORDS] = {
.feat_names = { .feat_names = {
[54] = "vmx-ins-outs", [54] = "vmx-ins-outs",
[55] = "vmx-true-ctls", [55] = "vmx-true-ctls",
[56] = "vmx-any-errcode",
}, },
.msr = { .msr = {
.index = MSR_IA32_VMX_BASIC, .index = MSR_IA32_VMX_BASIC,

1
target/i386/cpu.h
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@ -1039,6 +1039,7 @@ uint64_t x86_cpu_get_supported_feature_word(FeatureWord w,
#define MSR_VMX_BASIC_DUAL_MONITOR (1ULL << 49) #define MSR_VMX_BASIC_DUAL_MONITOR (1ULL << 49)
#define MSR_VMX_BASIC_INS_OUTS (1ULL << 54) #define MSR_VMX_BASIC_INS_OUTS (1ULL << 54)
#define MSR_VMX_BASIC_TRUE_CTLS (1ULL << 55) #define MSR_VMX_BASIC_TRUE_CTLS (1ULL << 55)
#define MSR_VMX_BASIC_ANY_ERRCODE (1ULL << 56)
#define MSR_VMX_MISC_PREEMPTION_TIMER_SHIFT_MASK 0x1Full #define MSR_VMX_MISC_PREEMPTION_TIMER_SHIFT_MASK 0x1Full
#define MSR_VMX_MISC_STORE_LMA (1ULL << 5) #define MSR_VMX_MISC_STORE_LMA (1ULL << 5)