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arm: Don't potentially overwrite input registers in add2, sub2. 

According to malc TCG will often genereate an add2/sub2/mul2 with low
half of the output in the same register as high half of one of the
inputs, so account for that.


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5847 c046a42c-6fe2-441c-8c8c-71466251a162
This commit is contained in:
balrog 2008-12-01 11:57:21 +00:00
parent 63d412465b
commit 0c9c3a9e3a
1 changed files with 13 additions and 4 deletions
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17
tcg/arm/tcg-target.c
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@ -295,10 +295,19 @@ static inline void tcg_out_dat_reg2(TCGContext *s,
int cond, int opc0, int opc1, int rd0, int rd1, int cond, int opc0, int opc1, int rd0, int rd1,
int rn0, int rn1, int rm0, int rm1, int shift) int rn0, int rn1, int rm0, int rm1, int shift)
{ {
tcg_out32(s, (cond << 28) | (0 << 25) | (opc0 << 21) | (1 << 20) | if (rd0 == rn1 || rd0 == rm1) {
(rn0 << 16) | (rd0 << 12) | shift | rm0); tcg_out32(s, (cond << 28) | (0 << 25) | (opc0 << 21) | (1 << 20) |
tcg_out32(s, (cond << 28) | (0 << 25) | (opc1 << 21) | (rn0 << 16) | (8 << 12) | shift | rm0);
(rn1 << 16) | (rd1 << 12) | shift | rm1); tcg_out32(s, (cond << 28) | (0 << 25) | (opc1 << 21) |
(rn1 << 16) | (rd1 << 12) | shift | rm1);
tcg_out_dat_reg(s, cond, ARITH_MOV,
rd0, 0, TCG_REG_R8, SHIFT_IMM_LSL(0));
} else {
tcg_out32(s, (cond << 28) | (0 << 25) | (opc0 << 21) | (1 << 20) |
(rn0 << 16) | (rd0 << 12) | shift | rm0);
tcg_out32(s, (cond << 28) | (0 << 25) | (opc1 << 21) |
(rn1 << 16) | (rd1 << 12) | shift | rm1);
}
} }
static inline void tcg_out_dat_imm(TCGContext *s, static inline void tcg_out_dat_imm(TCGContext *s,