target/riscv: Add csr support for svadu
Add ext_svadu property Add HADE field in *envcfg: * menvcfg.HADE is read-only zero if Svadu is not implemented. * henvcfg.HADE is read-only zero if menvcfg.HADE is zero. Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn> Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn> Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Message-ID: <20230224040852.37109-4-liweiwei@iscas.ac.cn> Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
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@ -450,6 +450,7 @@ struct RISCVCPUConfig {
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bool ext_zihintpause;
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bool ext_smstateen;
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bool ext_sstc;
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bool ext_svadu;
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bool ext_svinval;
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bool ext_svnapot;
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bool ext_svpbmt;
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@ -747,10 +747,12 @@ typedef enum RISCVException {
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#define MENVCFG_CBIE (3UL << 4)
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#define MENVCFG_CBCFE BIT(6)
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#define MENVCFG_CBZE BIT(7)
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#define MENVCFG_HADE (1ULL << 61)
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#define MENVCFG_PBMTE (1ULL << 62)
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#define MENVCFG_STCE (1ULL << 63)
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/* For RV32 */
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#define MENVCFGH_HADE BIT(29)
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#define MENVCFGH_PBMTE BIT(30)
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#define MENVCFGH_STCE BIT(31)
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@ -763,10 +765,12 @@ typedef enum RISCVException {
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#define HENVCFG_CBIE MENVCFG_CBIE
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#define HENVCFG_CBCFE MENVCFG_CBCFE
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#define HENVCFG_CBZE MENVCFG_CBZE
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#define HENVCFG_HADE MENVCFG_HADE
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#define HENVCFG_PBMTE MENVCFG_PBMTE
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#define HENVCFG_STCE MENVCFG_STCE
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/* For RV32 */
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#define HENVCFGH_HADE MENVCFGH_HADE
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#define HENVCFGH_PBMTE MENVCFGH_PBMTE
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#define HENVCFGH_STCE MENVCFGH_STCE
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@ -1890,7 +1890,8 @@ static RISCVException write_menvcfg(CPURISCVState *env, int csrno,
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if (riscv_cpu_mxl(env) == MXL_RV64) {
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mask |= (cfg->ext_svpbmt ? MENVCFG_PBMTE : 0) |
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(cfg->ext_sstc ? MENVCFG_STCE : 0);
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(cfg->ext_sstc ? MENVCFG_STCE : 0) |
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(cfg->ext_svadu ? MENVCFG_HADE : 0);
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}
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env->menvcfg = (env->menvcfg & ~mask) | (val & mask);
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@ -1909,7 +1910,8 @@ static RISCVException write_menvcfgh(CPURISCVState *env, int csrno,
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{
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RISCVCPUConfig *cfg = &env_archcpu(env)->cfg;
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uint64_t mask = (cfg->ext_svpbmt ? MENVCFG_PBMTE : 0) |
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(cfg->ext_sstc ? MENVCFG_STCE : 0);
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(cfg->ext_sstc ? MENVCFG_STCE : 0) |
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(cfg->ext_svadu ? MENVCFG_HADE : 0);
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uint64_t valh = (uint64_t)val << 32;
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env->menvcfg = (env->menvcfg & ~mask) | (valh & mask);
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@ -1959,8 +1961,10 @@ static RISCVException read_henvcfg(CPURISCVState *env, int csrno,
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/*
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* henvcfg.pbmte is read_only 0 when menvcfg.pbmte = 0
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* henvcfg.stce is read_only 0 when menvcfg.stce = 0
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* henvcfg.hade is read_only 0 when menvcfg.hade = 0
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*/
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*val = env->henvcfg & (~(HENVCFG_PBMTE | HENVCFG_STCE) | env->menvcfg);
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*val = env->henvcfg & (~(HENVCFG_PBMTE | HENVCFG_STCE | HENVCFG_HADE) |
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env->menvcfg);
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return RISCV_EXCP_NONE;
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}
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@ -1976,7 +1980,7 @@ static RISCVException write_henvcfg(CPURISCVState *env, int csrno,
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}
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if (riscv_cpu_mxl(env) == MXL_RV64) {
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mask |= env->menvcfg & (HENVCFG_PBMTE | HENVCFG_STCE);
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mask |= env->menvcfg & (HENVCFG_PBMTE | HENVCFG_STCE | HENVCFG_HADE);
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}
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env->henvcfg = (env->henvcfg & ~mask) | (val & mask);
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@ -1994,7 +1998,7 @@ static RISCVException read_henvcfgh(CPURISCVState *env, int csrno,
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return ret;
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}
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*val = (env->henvcfg & (~(HENVCFG_PBMTE | HENVCFG_STCE) |
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*val = (env->henvcfg & (~(HENVCFG_PBMTE | HENVCFG_STCE | HENVCFG_HADE) |
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env->menvcfg)) >> 32;
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return RISCV_EXCP_NONE;
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}
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@ -2002,7 +2006,8 @@ static RISCVException read_henvcfgh(CPURISCVState *env, int csrno,
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static RISCVException write_henvcfgh(CPURISCVState *env, int csrno,
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target_ulong val)
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{
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uint64_t mask = env->menvcfg & (HENVCFG_PBMTE | HENVCFG_STCE);
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uint64_t mask = env->menvcfg & (HENVCFG_PBMTE | HENVCFG_STCE |
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HENVCFG_HADE);
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uint64_t valh = (uint64_t)val << 32;
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RISCVException ret;
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