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target/mips: Add missing default_tcg_memop_mask 

Memory operations that are not already aligned, or otherwise
marked up, require addition of ctx->default_tcg_memop_mask.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
This commit is contained in:
Richard Henderson 2023-05-02 10:22:23 +01:00
parent 3ec02c1f0f
commit 0d5bede468
4 changed files with 42 additions and 28 deletions
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24
target/mips/tcg/micromips_translate.c.inc
View File

@ -977,20 +977,24 @@ static void gen_ldst_pair(DisasContext *ctx, uint32_t opc, int rd,
gen_reserved_instruction(ctx); gen_reserved_instruction(ctx);
return; return;
} }
tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, MO_TESL); tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, MO_TESL |
ctx->default_tcg_memop_mask);
gen_store_gpr(t1, rd); gen_store_gpr(t1, rd);
tcg_gen_movi_tl(t1, 4); tcg_gen_movi_tl(t1, 4);
gen_op_addr_add(ctx, t0, t0, t1); gen_op_addr_add(ctx, t0, t0, t1);
tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, MO_TESL); tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, MO_TESL |
ctx->default_tcg_memop_mask);
gen_store_gpr(t1, rd + 1); gen_store_gpr(t1, rd + 1);
break; break;
case SWP: case SWP:
gen_load_gpr(t1, rd); gen_load_gpr(t1, rd);
tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TEUL); tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TEUL |
ctx->default_tcg_memop_mask);
tcg_gen_movi_tl(t1, 4); tcg_gen_movi_tl(t1, 4);
gen_op_addr_add(ctx, t0, t0, t1); gen_op_addr_add(ctx, t0, t0, t1);
gen_load_gpr(t1, rd + 1); gen_load_gpr(t1, rd + 1);
tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TEUL); tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TEUL |
ctx->default_tcg_memop_mask);
break; break;
#ifdef TARGET_MIPS64 #ifdef TARGET_MIPS64
case LDP: case LDP:
@ -998,20 +1002,24 @@ static void gen_ldst_pair(DisasContext *ctx, uint32_t opc, int rd,
gen_reserved_instruction(ctx); gen_reserved_instruction(ctx);
return; return;
} }
tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, MO_TEUQ); tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, MO_TEUQ |
ctx->default_tcg_memop_mask);
gen_store_gpr(t1, rd); gen_store_gpr(t1, rd);
tcg_gen_movi_tl(t1, 8); tcg_gen_movi_tl(t1, 8);
gen_op_addr_add(ctx, t0, t0, t1); gen_op_addr_add(ctx, t0, t0, t1);
tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, MO_TEUQ); tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, MO_TEUQ |
ctx->default_tcg_memop_mask);
gen_store_gpr(t1, rd + 1); gen_store_gpr(t1, rd + 1);
break; break;
case SDP: case SDP:
gen_load_gpr(t1, rd); gen_load_gpr(t1, rd);
tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TEUQ); tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TEUQ |
ctx->default_tcg_memop_mask);
tcg_gen_movi_tl(t1, 8); tcg_gen_movi_tl(t1, 8);
gen_op_addr_add(ctx, t0, t0, t1); gen_op_addr_add(ctx, t0, t0, t1);
gen_load_gpr(t1, rd + 1); gen_load_gpr(t1, rd + 1);
tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TEUQ); tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TEUQ |
ctx->default_tcg_memop_mask);
break; break;
#endif #endif
} }

18
target/mips/tcg/mips16e_translate.c.inc
View File

@ -172,22 +172,26 @@ static void gen_mips16_save(DisasContext *ctx,
case 4: case 4:
gen_base_offset_addr(ctx, t0, 29, 12); gen_base_offset_addr(ctx, t0, 29, 12);
gen_load_gpr(t1, 7); gen_load_gpr(t1, 7);
tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TEUL); tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TEUL |
ctx->default_tcg_memop_mask);
/* Fall through */ /* Fall through */
case 3: case 3:
gen_base_offset_addr(ctx, t0, 29, 8); gen_base_offset_addr(ctx, t0, 29, 8);
gen_load_gpr(t1, 6); gen_load_gpr(t1, 6);
tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TEUL); tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TEUL |
ctx->default_tcg_memop_mask);
/* Fall through */ /* Fall through */
case 2: case 2:
gen_base_offset_addr(ctx, t0, 29, 4); gen_base_offset_addr(ctx, t0, 29, 4);
gen_load_gpr(t1, 5); gen_load_gpr(t1, 5);
tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TEUL); tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TEUL |
ctx->default_tcg_memop_mask);
/* Fall through */ /* Fall through */
case 1: case 1:
gen_base_offset_addr(ctx, t0, 29, 0); gen_base_offset_addr(ctx, t0, 29, 0);
gen_load_gpr(t1, 4); gen_load_gpr(t1, 4);
tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TEUL); tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TEUL |
ctx->default_tcg_memop_mask);
} }
gen_load_gpr(t0, 29); gen_load_gpr(t0, 29);
@ -196,7 +200,8 @@ static void gen_mips16_save(DisasContext *ctx,
tcg_gen_movi_tl(t2, -4); \ tcg_gen_movi_tl(t2, -4); \
gen_op_addr_add(ctx, t0, t0, t2); \ gen_op_addr_add(ctx, t0, t0, t2); \
gen_load_gpr(t1, reg); \ gen_load_gpr(t1, reg); \
tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TEUL); \ tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TEUL | \
ctx->default_tcg_memop_mask); \
} while (0) } while (0)
if (do_ra) { if (do_ra) {
@ -298,7 +303,8 @@ static void gen_mips16_restore(DisasContext *ctx,
#define DECR_AND_LOAD(reg) do { \ #define DECR_AND_LOAD(reg) do { \
tcg_gen_movi_tl(t2, -4); \ tcg_gen_movi_tl(t2, -4); \
gen_op_addr_add(ctx, t0, t0, t2); \ gen_op_addr_add(ctx, t0, t0, t2); \
tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, MO_TESL); \ tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, MO_TESL | \
ctx->default_tcg_memop_mask); \
gen_store_gpr(t1, reg); \ gen_store_gpr(t1, reg); \
} while (0) } while (0)

3
target/mips/tcg/mxu_translate.c
View File

@ -831,7 +831,8 @@ static void gen_mxu_s32ldd_s32lddr(DisasContext *ctx)
tcg_gen_ori_tl(t1, t1, 0xFFFFF000); tcg_gen_ori_tl(t1, t1, 0xFFFFF000);
} }
tcg_gen_add_tl(t1, t0, t1); tcg_gen_add_tl(t1, t0, t1);
tcg_gen_qemu_ld_tl(t1, t1, ctx->mem_idx, MO_TESL ^ (sel * MO_BSWAP)); tcg_gen_qemu_ld_tl(t1, t1, ctx->mem_idx, (MO_TESL ^ (sel * MO_BSWAP)) |
ctx->default_tcg_memop_mask);
gen_store_mxu_gpr(t1, XRa); gen_store_mxu_gpr(t1, XRa);
} }

25
target/mips/tcg/nanomips_translate.c.inc
View File

@ -2641,52 +2641,49 @@ static void gen_p_lsx(DisasContext *ctx, int rd, int rs, int rt)
switch (extract32(ctx->opcode, 7, 4)) { switch (extract32(ctx->opcode, 7, 4)) {
case NM_LBX: case NM_LBX:
tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, MO_SB);
MO_SB);
gen_store_gpr(t0, rd); gen_store_gpr(t0, rd);
break; break;
case NM_LHX: case NM_LHX:
/*case NM_LHXS:*/ /*case NM_LHXS:*/
tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx,
MO_TESW); MO_TESW | ctx->default_tcg_memop_mask);
gen_store_gpr(t0, rd); gen_store_gpr(t0, rd);
break; break;
case NM_LWX: case NM_LWX:
/*case NM_LWXS:*/ /*case NM_LWXS:*/
tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx,
MO_TESL); MO_TESL | ctx->default_tcg_memop_mask);
gen_store_gpr(t0, rd); gen_store_gpr(t0, rd);
break; break;
case NM_LBUX: case NM_LBUX:
tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, MO_UB);
MO_UB);
gen_store_gpr(t0, rd); gen_store_gpr(t0, rd);
break; break;
case NM_LHUX: case NM_LHUX:
/*case NM_LHUXS:*/ /*case NM_LHUXS:*/
tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx,
MO_TEUW); MO_TEUW | ctx->default_tcg_memop_mask);
gen_store_gpr(t0, rd); gen_store_gpr(t0, rd);
break; break;
case NM_SBX: case NM_SBX:
check_nms(ctx); check_nms(ctx);
gen_load_gpr(t1, rd); gen_load_gpr(t1, rd);
tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_8);
MO_8);
break; break;
case NM_SHX: case NM_SHX:
/*case NM_SHXS:*/ /*case NM_SHXS:*/
check_nms(ctx); check_nms(ctx);
gen_load_gpr(t1, rd); gen_load_gpr(t1, rd);
tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx,
MO_TEUW); MO_TEUW | ctx->default_tcg_memop_mask);
break; break;
case NM_SWX: case NM_SWX:
/*case NM_SWXS:*/ /*case NM_SWXS:*/
check_nms(ctx); check_nms(ctx);
gen_load_gpr(t1, rd); gen_load_gpr(t1, rd);
tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx,
MO_TEUL); MO_TEUL | ctx->default_tcg_memop_mask);
break; break;
case NM_LWC1X: case NM_LWC1X:
/*case NM_LWC1XS:*/ /*case NM_LWC1XS:*/
@ -3739,7 +3736,8 @@ static int decode_nanomips_32_48_opc(CPUMIPSState *env, DisasContext *ctx)
addr_off); addr_off);
tcg_gen_movi_tl(t0, addr); tcg_gen_movi_tl(t0, addr);
tcg_gen_qemu_ld_tl(cpu_gpr[rt], t0, ctx->mem_idx, MO_TESL); tcg_gen_qemu_ld_tl(cpu_gpr[rt], t0, ctx->mem_idx,
MO_TESL | ctx->default_tcg_memop_mask);
} }
break; break;
case NM_SWPC48: case NM_SWPC48:
@ -3755,7 +3753,8 @@ static int decode_nanomips_32_48_opc(CPUMIPSState *env, DisasContext *ctx)
tcg_gen_movi_tl(t0, addr); tcg_gen_movi_tl(t0, addr);
gen_load_gpr(t1, rt); gen_load_gpr(t1, rt);
tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TEUL); tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx,
MO_TEUL | ctx->default_tcg_memop_mask);
} }
break; break;
default: default: