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riscv: sifive: Implement PRCI model for FU540 

This adds a simple PRCI model for FU540 (sifive_u). It has different
register layout from the existing PRCI model for FE310 (sifive_e).

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
This commit is contained in:
Bin Meng 2019-09-06 09:20:08 -07:00 committed by Palmer Dabbelt
parent ef965ce239
commit 0d95299468
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GPG Key ID: EF4CA1502CCBAB41
3 changed files with 251 additions and 0 deletions
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1
hw/riscv/Makefile.objs
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@ -8,6 +8,7 @@ obj-$(CONFIG_SIFIVE) += sifive_gpio.o
obj-$(CONFIG_SIFIVE) += sifive_plic.o
obj-$(CONFIG_SIFIVE) += sifive_test.o
obj-$(CONFIG_SIFIVE_U) += sifive_u.o
obj-$(CONFIG_SIFIVE_U) += sifive_u_prci.o
obj-$(CONFIG_SIFIVE) += sifive_uart.o
obj-$(CONFIG_SPIKE) += spike.o
obj-$(CONFIG_RISCV_VIRT) += virt.o

169
hw/riscv/sifive_u_prci.c Normal file
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@ -0,0 +1,169 @@
/*
* QEMU SiFive U PRCI (Power, Reset, Clock, Interrupt)
*
* Copyright (c) 2019 Bin Meng <bmeng.cn@gmail.com>
*
* Simple model of the PRCI to emulate register reads made by the SDK BSP
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2 or later, as published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program. If not, see <http://www.gnu.org/licenses/>.
*/
#include "qemu/osdep.h"
#include "hw/sysbus.h"
#include "qemu/log.h"
#include "qemu/module.h"
#include "hw/riscv/sifive_u_prci.h"
static uint64_t sifive_u_prci_read(void *opaque, hwaddr addr, unsigned int size)
{
SiFiveUPRCIState *s = opaque;
switch (addr) {
case SIFIVE_U_PRCI_HFXOSCCFG:
return s->hfxosccfg;
case SIFIVE_U_PRCI_COREPLLCFG0:
return s->corepllcfg0;
case SIFIVE_U_PRCI_DDRPLLCFG0:
return s->ddrpllcfg0;
case SIFIVE_U_PRCI_DDRPLLCFG1:
return s->ddrpllcfg1;
case SIFIVE_U_PRCI_GEMGXLPLLCFG0:
return s->gemgxlpllcfg0;
case SIFIVE_U_PRCI_GEMGXLPLLCFG1:
return s->gemgxlpllcfg1;
case SIFIVE_U_PRCI_CORECLKSEL:
return s->coreclksel;
case SIFIVE_U_PRCI_DEVICESRESET:
return s->devicesreset;
case SIFIVE_U_PRCI_CLKMUXSTATUS:
return s->clkmuxstatus;
}
qemu_log_mask(LOG_GUEST_ERROR, "%s: read: addr=0x%" HWADDR_PRIx "\n",
__func__, addr);
return 0;
}
static void sifive_u_prci_write(void *opaque, hwaddr addr,
uint64_t val64, unsigned int size)
{
SiFiveUPRCIState *s = opaque;
uint32_t val32 = (uint32_t)val64;
switch (addr) {
case SIFIVE_U_PRCI_HFXOSCCFG:
s->hfxosccfg = val32;
/* OSC stays ready */
s->hfxosccfg |= SIFIVE_U_PRCI_HFXOSCCFG_RDY;
break;
case SIFIVE_U_PRCI_COREPLLCFG0:
s->corepllcfg0 = val32;
/* internal feedback */
s->corepllcfg0 |= SIFIVE_U_PRCI_PLLCFG0_FSE;
/* PLL stays locked */
s->corepllcfg0 |= SIFIVE_U_PRCI_PLLCFG0_LOCK;
break;
case SIFIVE_U_PRCI_DDRPLLCFG0:
s->ddrpllcfg0 = val32;
/* internal feedback */
s->ddrpllcfg0 |= SIFIVE_U_PRCI_PLLCFG0_FSE;
/* PLL stays locked */
s->ddrpllcfg0 |= SIFIVE_U_PRCI_PLLCFG0_LOCK;
break;
case SIFIVE_U_PRCI_DDRPLLCFG1:
s->ddrpllcfg1 = val32;
break;
case SIFIVE_U_PRCI_GEMGXLPLLCFG0:
s->gemgxlpllcfg0 = val32;
/* internal feedback */
s->gemgxlpllcfg0 |= SIFIVE_U_PRCI_PLLCFG0_FSE;
/* PLL stays locked */
s->gemgxlpllcfg0 |= SIFIVE_U_PRCI_PLLCFG0_LOCK;
break;
case SIFIVE_U_PRCI_GEMGXLPLLCFG1:
s->gemgxlpllcfg1 = val32;
break;
case SIFIVE_U_PRCI_CORECLKSEL:
s->coreclksel = val32;
break;
case SIFIVE_U_PRCI_DEVICESRESET:
s->devicesreset = val32;
break;
case SIFIVE_U_PRCI_CLKMUXSTATUS:
s->clkmuxstatus = val32;
break;
default:
qemu_log_mask(LOG_GUEST_ERROR, "%s: bad write: addr=0x%" HWADDR_PRIx
" v=0x%x\n", __func__, addr, val32);
}
}
static const MemoryRegionOps sifive_u_prci_ops = {
.read = sifive_u_prci_read,
.write = sifive_u_prci_write,
.endianness = DEVICE_NATIVE_ENDIAN,
.valid = {
.min_access_size = 4,
.max_access_size = 4
}
};
static void sifive_u_prci_realize(DeviceState *dev, Error **errp)
{
SiFiveUPRCIState *s = SIFIVE_U_PRCI(dev);
memory_region_init_io(&s->mmio, OBJECT(dev), &sifive_u_prci_ops, s,
TYPE_SIFIVE_U_PRCI, SIFIVE_U_PRCI_REG_SIZE);
sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->mmio);
}
static void sifive_u_prci_reset(DeviceState *dev)
{
SiFiveUPRCIState *s = SIFIVE_U_PRCI(dev);
/* Initialize register to power-on-reset values */
s->hfxosccfg = SIFIVE_U_PRCI_HFXOSCCFG_RDY | SIFIVE_U_PRCI_HFXOSCCFG_EN;
s->corepllcfg0 = SIFIVE_U_PRCI_PLLCFG0_DIVR | SIFIVE_U_PRCI_PLLCFG0_DIVF |
SIFIVE_U_PRCI_PLLCFG0_DIVQ | SIFIVE_U_PRCI_PLLCFG0_FSE |
SIFIVE_U_PRCI_PLLCFG0_LOCK;
s->ddrpllcfg0 = SIFIVE_U_PRCI_PLLCFG0_DIVR | SIFIVE_U_PRCI_PLLCFG0_DIVF |
SIFIVE_U_PRCI_PLLCFG0_DIVQ | SIFIVE_U_PRCI_PLLCFG0_FSE |
SIFIVE_U_PRCI_PLLCFG0_LOCK;
s->gemgxlpllcfg0 = SIFIVE_U_PRCI_PLLCFG0_DIVR | SIFIVE_U_PRCI_PLLCFG0_DIVF |
SIFIVE_U_PRCI_PLLCFG0_DIVQ | SIFIVE_U_PRCI_PLLCFG0_FSE |
SIFIVE_U_PRCI_PLLCFG0_LOCK;
s->coreclksel = SIFIVE_U_PRCI_CORECLKSEL_HFCLK;
}
static void sifive_u_prci_class_init(ObjectClass *klass, void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
dc->realize = sifive_u_prci_realize;
dc->reset = sifive_u_prci_reset;
}
static const TypeInfo sifive_u_prci_info = {
.name = TYPE_SIFIVE_U_PRCI,
.parent = TYPE_SYS_BUS_DEVICE,
.instance_size = sizeof(SiFiveUPRCIState),
.class_init = sifive_u_prci_class_init,
};
static void sifive_u_prci_register_types(void)
{
type_register_static(&sifive_u_prci_info);
}
type_init(sifive_u_prci_register_types)

81
include/hw/riscv/sifive_u_prci.h Normal file
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@ -0,0 +1,81 @@
/*
* QEMU SiFive U PRCI (Power, Reset, Clock, Interrupt) interface
*
* Copyright (c) 2019 Bin Meng <bmeng.cn@gmail.com>
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2 or later, as published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program. If not, see <http://www.gnu.org/licenses/>.
*/
#ifndef HW_SIFIVE_U_PRCI_H
#define HW_SIFIVE_U_PRCI_H
#define SIFIVE_U_PRCI_HFXOSCCFG 0x00
#define SIFIVE_U_PRCI_COREPLLCFG0 0x04
#define SIFIVE_U_PRCI_DDRPLLCFG0 0x0C
#define SIFIVE_U_PRCI_DDRPLLCFG1 0x10
#define SIFIVE_U_PRCI_GEMGXLPLLCFG0 0x1C
#define SIFIVE_U_PRCI_GEMGXLPLLCFG1 0x20
#define SIFIVE_U_PRCI_CORECLKSEL 0x24
#define SIFIVE_U_PRCI_DEVICESRESET 0x28
#define SIFIVE_U_PRCI_CLKMUXSTATUS 0x2C
/*
* Current FU540-C000 manual says ready bit is at bit 29, but
* freedom-u540-c000-bootloader codes (ux00prci.h) says it is at bit 31.
* We have to trust the actual code that works.
*
* see https://github.com/sifive/freedom-u540-c000-bootloader
*/
#define SIFIVE_U_PRCI_HFXOSCCFG_EN (1 << 30)
#define SIFIVE_U_PRCI_HFXOSCCFG_RDY (1 << 31)
/* xxxPLLCFG0 register bits */
#define SIFIVE_U_PRCI_PLLCFG0_DIVR (1 << 0)
#define SIFIVE_U_PRCI_PLLCFG0_DIVF (31 << 6)
#define SIFIVE_U_PRCI_PLLCFG0_DIVQ (3 << 15)
#define SIFIVE_U_PRCI_PLLCFG0_FSE (1 << 25)
#define SIFIVE_U_PRCI_PLLCFG0_LOCK (1 << 31)
/* xxxPLLCFG1 register bits */
#define SIFIVE_U_PRCI_PLLCFG1_CKE (1 << 24)
/* coreclksel register bits */
#define SIFIVE_U_PRCI_CORECLKSEL_HFCLK (1 << 0)
#define SIFIVE_U_PRCI_REG_SIZE 0x1000
#define TYPE_SIFIVE_U_PRCI "riscv.sifive.u.prci"
#define SIFIVE_U_PRCI(obj) \
OBJECT_CHECK(SiFiveUPRCIState, (obj), TYPE_SIFIVE_U_PRCI)
typedef struct SiFiveUPRCIState {
/*< private >*/
SysBusDevice parent_obj;
/*< public >*/
MemoryRegion mmio;
uint32_t hfxosccfg;
uint32_t corepllcfg0;
uint32_t ddrpllcfg0;
uint32_t ddrpllcfg1;
uint32_t gemgxlpllcfg0;
uint32_t gemgxlpllcfg1;
uint32_t coreclksel;
uint32_t devicesreset;
uint32_t clkmuxstatus;
} SiFiveUPRCIState;
#endif /* HW_SIFIVE_U_PRCI_H */