spapr: Reorganize CPU dt generation code
Reorganize CPU device tree generation code so that it be reused from hotplug path. CPU dt entries are now generated from spapr_finalize_fdt() instead of spapr_create_fdt_skel(). Note: This is how the split-up looks like now: Boot path --------- spapr_finalize_fdt spapr_populate_cpus_dt_node spapr_populate_cpu_dt spapr_fixup_cpu_numa_dt spapr_fixup_cpu_smt_dt ibm,cas path ------------ spapr_h_cas_compose_response spapr_fixup_cpu_dt spapr_fixup_cpu_numa_dt spapr_fixup_cpu_smt_dt Signed-off-by: Bharata B Rao <bharata@linux.vnet.ibm.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: Alexander Graf <agraf@suse.de>
This commit is contained in:
Bharata B Rao
Alexander Graf
parent
8487d12318
commit
0da6f3fef9
284
hw/ppc/spapr.c
284
hw/ppc/spapr.c
@ -165,6 +165,27 @@ static int spapr_fixup_cpu_smt_dt(void *fdt, int offset, PowerPCCPU *cpu,
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return ret;
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}
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static int spapr_fixup_cpu_numa_dt(void *fdt, int offset, CPUState *cs)
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{
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int ret = 0;
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PowerPCCPU *cpu = POWERPC_CPU(cs);
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int index = ppc_get_vcpu_dt_id(cpu);
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uint32_t associativity[] = {cpu_to_be32(0x5),
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cpu_to_be32(0x0),
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cpu_to_be32(0x0),
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cpu_to_be32(0x0),
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cpu_to_be32(cs->numa_node),
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cpu_to_be32(index)};
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/* Advertise NUMA via ibm,associativity */
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if (nb_numa_nodes > 1) {
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ret = fdt_setprop(fdt, offset, "ibm,associativity", associativity,
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sizeof(associativity));
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}
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return ret;
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}
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static int spapr_fixup_cpu_dt(void *fdt, sPAPRMachineState *spapr)
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{
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int ret = 0, offset, cpus_offset;
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@ -177,12 +198,6 @@ static int spapr_fixup_cpu_dt(void *fdt, sPAPRMachineState *spapr)
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PowerPCCPU *cpu = POWERPC_CPU(cs);
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DeviceClass *dc = DEVICE_GET_CLASS(cs);
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int index = ppc_get_vcpu_dt_id(cpu);
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uint32_t associativity[] = {cpu_to_be32(0x5),
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cpu_to_be32(0x0),
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cpu_to_be32(0x0),
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cpu_to_be32(0x0),
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cpu_to_be32(cs->numa_node),
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cpu_to_be32(index)};
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if ((index % smt) != 0) {
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continue;
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@ -206,20 +221,17 @@ static int spapr_fixup_cpu_dt(void *fdt, sPAPRMachineState *spapr)
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}
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}
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if (nb_numa_nodes > 1) {
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ret = fdt_setprop(fdt, offset, "ibm,associativity", associativity,
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sizeof(associativity));
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if (ret < 0) {
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return ret;
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}
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}
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ret = fdt_setprop(fdt, offset, "ibm,pft-size",
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pft_size_prop, sizeof(pft_size_prop));
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if (ret < 0) {
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return ret;
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}
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ret = spapr_fixup_cpu_numa_dt(fdt, offset, cs);
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if (ret < 0) {
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return ret;
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}
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ret = spapr_fixup_cpu_smt_dt(fdt, offset, cpu,
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ppc_get_compat_smt_threads(cpu));
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if (ret < 0) {
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@ -302,18 +314,13 @@ static void *spapr_create_fdt_skel(hwaddr initrd_base,
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uint32_t epow_irq)
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{
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void *fdt;
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CPUState *cs;
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uint32_t start_prop = cpu_to_be32(initrd_base);
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uint32_t end_prop = cpu_to_be32(initrd_base + initrd_size);
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GString *hypertas = g_string_sized_new(256);
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GString *qemu_hypertas = g_string_sized_new(256);
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uint32_t refpoints[] = {cpu_to_be32(0x4), cpu_to_be32(0x4)};
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uint32_t interrupt_server_ranges_prop[] = {0, cpu_to_be32(max_cpus)};
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int smt = kvmppc_smt_threads();
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unsigned char vec5[] = {0x0, 0x0, 0x0, 0x0, 0x0, 0x80};
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QemuOpts *opts = qemu_opts_find(qemu_find_opts("smp-opts"), NULL);
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unsigned sockets = opts ? qemu_opt_get_number(opts, "sockets", 0) : 0;
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uint32_t cpus_per_socket = sockets ? (smp_cpus / sockets) : 1;
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char *buf;
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add_str(hypertas, "hcall-pft");
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@ -399,107 +406,6 @@ static void *spapr_create_fdt_skel(hwaddr initrd_base,
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_FDT((fdt_end_node(fdt)));
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/* cpus */
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_FDT((fdt_begin_node(fdt, "cpus")));
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_FDT((fdt_property_cell(fdt, "#address-cells", 0x1)));
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_FDT((fdt_property_cell(fdt, "#size-cells", 0x0)));
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CPU_FOREACH(cs) {
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PowerPCCPU *cpu = POWERPC_CPU(cs);
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CPUPPCState *env = &cpu->env;
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DeviceClass *dc = DEVICE_GET_CLASS(cs);
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PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cs);
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int index = ppc_get_vcpu_dt_id(cpu);
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char *nodename;
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uint32_t segs[] = {cpu_to_be32(28), cpu_to_be32(40),
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0xffffffff, 0xffffffff};
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uint32_t tbfreq = kvm_enabled() ? kvmppc_get_tbfreq() : TIMEBASE_FREQ;
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uint32_t cpufreq = kvm_enabled() ? kvmppc_get_clockfreq() : 1000000000;
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uint32_t page_sizes_prop[64];
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size_t page_sizes_prop_size;
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if ((index % smt) != 0) {
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continue;
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}
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nodename = g_strdup_printf("%s@%x", dc->fw_name, index);
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_FDT((fdt_begin_node(fdt, nodename)));
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g_free(nodename);
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_FDT((fdt_property_cell(fdt, "reg", index)));
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_FDT((fdt_property_string(fdt, "device_type", "cpu")));
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_FDT((fdt_property_cell(fdt, "cpu-version", env->spr[SPR_PVR])));
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_FDT((fdt_property_cell(fdt, "d-cache-block-size",
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env->dcache_line_size)));
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_FDT((fdt_property_cell(fdt, "d-cache-line-size",
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env->dcache_line_size)));
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_FDT((fdt_property_cell(fdt, "i-cache-block-size",
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env->icache_line_size)));
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_FDT((fdt_property_cell(fdt, "i-cache-line-size",
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env->icache_line_size)));
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if (pcc->l1_dcache_size) {
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_FDT((fdt_property_cell(fdt, "d-cache-size", pcc->l1_dcache_size)));
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} else {
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fprintf(stderr, "Warning: Unknown L1 dcache size for cpu\n");
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}
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if (pcc->l1_icache_size) {
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_FDT((fdt_property_cell(fdt, "i-cache-size", pcc->l1_icache_size)));
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} else {
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fprintf(stderr, "Warning: Unknown L1 icache size for cpu\n");
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}
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_FDT((fdt_property_cell(fdt, "timebase-frequency", tbfreq)));
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_FDT((fdt_property_cell(fdt, "clock-frequency", cpufreq)));
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_FDT((fdt_property_cell(fdt, "ibm,slb-size", env->slb_nr)));
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_FDT((fdt_property_string(fdt, "status", "okay")));
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_FDT((fdt_property(fdt, "64-bit", NULL, 0)));
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if (env->spr_cb[SPR_PURR].oea_read) {
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_FDT((fdt_property(fdt, "ibm,purr", NULL, 0)));
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}
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if (env->mmu_model & POWERPC_MMU_1TSEG) {
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_FDT((fdt_property(fdt, "ibm,processor-segment-sizes",
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segs, sizeof(segs))));
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}
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/* Advertise VMX/VSX (vector extensions) if available
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* 0 / no property == no vector extensions
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* 1 == VMX / Altivec available
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* 2 == VSX available */
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if (env->insns_flags & PPC_ALTIVEC) {
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uint32_t vmx = (env->insns_flags2 & PPC2_VSX) ? 2 : 1;
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_FDT((fdt_property_cell(fdt, "ibm,vmx", vmx)));
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}
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/* Advertise DFP (Decimal Floating Point) if available
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* 0 / no property == no DFP
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* 1 == DFP available */
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if (env->insns_flags2 & PPC2_DFP) {
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_FDT((fdt_property_cell(fdt, "ibm,dfp", 1)));
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}
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page_sizes_prop_size = create_page_sizes_prop(env, page_sizes_prop,
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sizeof(page_sizes_prop));
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if (page_sizes_prop_size) {
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_FDT((fdt_property(fdt, "ibm,segment-page-sizes",
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page_sizes_prop, page_sizes_prop_size)));
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}
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_FDT((fdt_property_cell(fdt, "ibm,chip-id",
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cs->cpu_index / cpus_per_socket)));
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_FDT((fdt_end_node(fdt)));
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}
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_FDT((fdt_end_node(fdt)));
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/* RTAS */
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_FDT((fdt_begin_node(fdt, "rtas")));
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@ -700,6 +606,137 @@ static int spapr_populate_memory(sPAPRMachineState *spapr, void *fdt)
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return 0;
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}
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static void spapr_populate_cpu_dt(CPUState *cs, void *fdt, int offset,
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sPAPRMachineState *spapr)
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{
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PowerPCCPU *cpu = POWERPC_CPU(cs);
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CPUPPCState *env = &cpu->env;
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PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cs);
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int index = ppc_get_vcpu_dt_id(cpu);
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uint32_t segs[] = {cpu_to_be32(28), cpu_to_be32(40),
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0xffffffff, 0xffffffff};
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uint32_t tbfreq = kvm_enabled() ? kvmppc_get_tbfreq() : TIMEBASE_FREQ;
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uint32_t cpufreq = kvm_enabled() ? kvmppc_get_clockfreq() : 1000000000;
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uint32_t page_sizes_prop[64];
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size_t page_sizes_prop_size;
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QemuOpts *opts = qemu_opts_find(qemu_find_opts("smp-opts"), NULL);
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unsigned sockets = opts ? qemu_opt_get_number(opts, "sockets", 0) : 0;
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uint32_t cpus_per_socket = sockets ? (smp_cpus / sockets) : 1;
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uint32_t pft_size_prop[] = {0, cpu_to_be32(spapr->htab_shift)};
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_FDT((fdt_setprop_cell(fdt, offset, "reg", index)));
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_FDT((fdt_setprop_string(fdt, offset, "device_type", "cpu")));
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_FDT((fdt_setprop_cell(fdt, offset, "cpu-version", env->spr[SPR_PVR])));
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_FDT((fdt_setprop_cell(fdt, offset, "d-cache-block-size",
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env->dcache_line_size)));
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_FDT((fdt_setprop_cell(fdt, offset, "d-cache-line-size",
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env->dcache_line_size)));
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_FDT((fdt_setprop_cell(fdt, offset, "i-cache-block-size",
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env->icache_line_size)));
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_FDT((fdt_setprop_cell(fdt, offset, "i-cache-line-size",
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env->icache_line_size)));
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if (pcc->l1_dcache_size) {
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_FDT((fdt_setprop_cell(fdt, offset, "d-cache-size",
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pcc->l1_dcache_size)));
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} else {
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fprintf(stderr, "Warning: Unknown L1 dcache size for cpu\n");
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}
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if (pcc->l1_icache_size) {
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_FDT((fdt_setprop_cell(fdt, offset, "i-cache-size",
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pcc->l1_icache_size)));
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} else {
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fprintf(stderr, "Warning: Unknown L1 icache size for cpu\n");
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}
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_FDT((fdt_setprop_cell(fdt, offset, "timebase-frequency", tbfreq)));
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_FDT((fdt_setprop_cell(fdt, offset, "clock-frequency", cpufreq)));
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_FDT((fdt_setprop_cell(fdt, offset, "ibm,slb-size", env->slb_nr)));
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_FDT((fdt_setprop_string(fdt, offset, "status", "okay")));
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_FDT((fdt_setprop(fdt, offset, "64-bit", NULL, 0)));
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if (env->spr_cb[SPR_PURR].oea_read) {
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_FDT((fdt_setprop(fdt, offset, "ibm,purr", NULL, 0)));
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}
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if (env->mmu_model & POWERPC_MMU_1TSEG) {
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_FDT((fdt_setprop(fdt, offset, "ibm,processor-segment-sizes",
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segs, sizeof(segs))));
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}
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/* Advertise VMX/VSX (vector extensions) if available
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* 0 / no property == no vector extensions
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* 1 == VMX / Altivec available
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* 2 == VSX available */
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if (env->insns_flags & PPC_ALTIVEC) {
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uint32_t vmx = (env->insns_flags2 & PPC2_VSX) ? 2 : 1;
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_FDT((fdt_setprop_cell(fdt, offset, "ibm,vmx", vmx)));
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}
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/* Advertise DFP (Decimal Floating Point) if available
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* 0 / no property == no DFP
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* 1 == DFP available */
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if (env->insns_flags2 & PPC2_DFP) {
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_FDT((fdt_setprop_cell(fdt, offset, "ibm,dfp", 1)));
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}
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page_sizes_prop_size = create_page_sizes_prop(env, page_sizes_prop,
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sizeof(page_sizes_prop));
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if (page_sizes_prop_size) {
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_FDT((fdt_setprop(fdt, offset, "ibm,segment-page-sizes",
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page_sizes_prop, page_sizes_prop_size)));
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}
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_FDT((fdt_setprop_cell(fdt, offset, "ibm,chip-id",
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cs->cpu_index / cpus_per_socket)));
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_FDT((fdt_setprop(fdt, offset, "ibm,pft-size",
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pft_size_prop, sizeof(pft_size_prop))));
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_FDT(spapr_fixup_cpu_numa_dt(fdt, offset, cs));
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_FDT(spapr_fixup_cpu_smt_dt(fdt, offset, cpu,
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ppc_get_compat_smt_threads(cpu)));
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}
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static void spapr_populate_cpus_dt_node(void *fdt, sPAPRMachineState *spapr)
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{
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CPUState *cs;
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int cpus_offset;
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char *nodename;
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int smt = kvmppc_smt_threads();
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cpus_offset = fdt_add_subnode(fdt, 0, "cpus");
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_FDT(cpus_offset);
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_FDT((fdt_setprop_cell(fdt, cpus_offset, "#address-cells", 0x1)));
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_FDT((fdt_setprop_cell(fdt, cpus_offset, "#size-cells", 0x0)));
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/*
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* We walk the CPUs in reverse order to ensure that CPU DT nodes
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* created by fdt_add_subnode() end up in the right order in FDT
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* for the guest kernel the enumerate the CPUs correctly.
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*/
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CPU_FOREACH_REVERSE(cs) {
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PowerPCCPU *cpu = POWERPC_CPU(cs);
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int index = ppc_get_vcpu_dt_id(cpu);
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DeviceClass *dc = DEVICE_GET_CLASS(cs);
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int offset;
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if ((index % smt) != 0) {
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continue;
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}
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nodename = g_strdup_printf("%s@%x", dc->fw_name, index);
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offset = fdt_add_subnode(fdt, cpus_offset, nodename);
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g_free(nodename);
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_FDT(offset);
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spapr_populate_cpu_dt(cs, fdt, offset, spapr);
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}
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}
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static void spapr_finalize_fdt(sPAPRMachineState *spapr,
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hwaddr fdt_addr,
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hwaddr rtas_addr,
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@ -745,11 +782,8 @@ static void spapr_finalize_fdt(sPAPRMachineState *spapr,
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fprintf(stderr, "Couldn't set up RTAS device tree properties\n");
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}
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/* Advertise NUMA via ibm,associativity */
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ret = spapr_fixup_cpu_dt(fdt, spapr);
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if (ret < 0) {
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fprintf(stderr, "Couldn't finalize CPU device tree properties\n");
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}
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/* cpus */
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spapr_populate_cpus_dt_node(fdt, spapr);
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bootlist = get_boot_devices_list(&cb, true);
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if (cb && bootlist) {
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