tests/qtest/libqos/e1000e: Use e1000_regs.h
The register definitions in tests/qtest/libqos/e1000e.c had names different from hw/net/e1000_regs.h, which made it hard to understand what test codes corresponds to the implementation. Use hw/net/e1000_regs.h from tests/qtest/libqos/e1000e.c to remove these duplications. E1000E_CTRL_EXT_TXLSFLOW is removed from E1000E_CTRL_EXT settings because hw/net/e1000_regs.h does not have the definition and it is for TCP segmentation offload, which does not matter for the implemented tests. Signed-off-by: Akihiko Odaki <akihiko.odaki@daynix.com> Message-Id: <20221013055245.28102-1-akihiko.odaki@daynix.com> Signed-off-by: Thomas Huth <thuth@redhat.com>
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@ -793,6 +793,7 @@
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#define E1000_CTRL_EXT_ASDCHK 0x00001000 /* auto speed detection check */
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#define E1000_CTRL_EXT_EE_RST 0x00002000 /* EEPROM reset */
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#define E1000_CTRL_EXT_LINK_EN 0x00010000 /* enable link status from external LINK_0 and LINK_1 pins */
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#define E1000_CTRL_EXT_DRV_LOAD 0x10000000 /* Driver loaded bit for FW */
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#define E1000_CTRL_EXT_EIAME 0x01000000
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#define E1000_CTRL_EXT_IAME 0x08000000 /* Int ACK Auto-mask */
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#define E1000_CTRL_EXT_PBA_CLR 0x80000000 /* PBA Clear */
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@ -17,6 +17,7 @@
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*/
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#include "qemu/osdep.h"
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#include "hw/net/e1000_regs.h"
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#include "../libqtest.h"
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#include "pci-pc.h"
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#include "qemu/sockets.h"
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@ -27,49 +28,13 @@
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#include "qgraph.h"
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#include "e1000e.h"
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#define E1000E_IMS (0x00d0)
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#define E1000E_IVAR_TEST_CFG \
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(E1000E_RX0_MSG_ID | E1000_IVAR_INT_ALLOC_VALID | \
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((E1000E_TX0_MSG_ID | E1000_IVAR_INT_ALLOC_VALID) << 8) | \
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((E1000E_OTHER_MSG_ID | E1000_IVAR_INT_ALLOC_VALID) << 16) | \
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E1000_IVAR_TX_INT_EVERY_WB)
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#define E1000E_STATUS (0x0008)
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#define E1000E_STATUS_LU BIT(1)
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#define E1000E_STATUS_ASDV1000 BIT(9)
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#define E1000E_CTRL (0x0000)
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#define E1000E_CTRL_RESET BIT(26)
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#define E1000E_RCTL (0x0100)
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#define E1000E_RCTL_EN BIT(1)
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#define E1000E_RCTL_UPE BIT(3)
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#define E1000E_RCTL_MPE BIT(4)
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#define E1000E_RFCTL (0x5008)
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#define E1000E_RFCTL_EXTEN BIT(15)
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#define E1000E_TCTL (0x0400)
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#define E1000E_TCTL_EN BIT(1)
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#define E1000E_CTRL_EXT (0x0018)
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#define E1000E_CTRL_EXT_DRV_LOAD BIT(28)
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#define E1000E_CTRL_EXT_TXLSFLOW BIT(22)
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#define E1000E_IVAR (0x00E4)
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#define E1000E_IVAR_TEST_CFG ((E1000E_RX0_MSG_ID << 0) | BIT(3) | \
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(E1000E_TX0_MSG_ID << 8) | BIT(11) | \
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(E1000E_OTHER_MSG_ID << 16) | BIT(19) | \
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BIT(31))
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#define E1000E_RING_LEN (0x1000)
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#define E1000E_TDBAL (0x3800)
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#define E1000E_TDBAH (0x3804)
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#define E1000E_TDH (0x3810)
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#define E1000E_RDBAL (0x2800)
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#define E1000E_RDBAH (0x2804)
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#define E1000E_RDH (0x2810)
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#define E1000E_TXD_LEN (16)
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#define E1000E_RXD_LEN (16)
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#define E1000E_RING_LEN (0x1000)
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static void e1000e_macreg_write(QE1000E *d, uint32_t reg, uint32_t val)
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{
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@ -87,30 +52,34 @@ void e1000e_tx_ring_push(QE1000E *d, void *descr)
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{
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QE1000E_PCI *d_pci = container_of(d, QE1000E_PCI, e1000e);
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uint32_t tail = e1000e_macreg_read(d, E1000E_TDT);
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uint32_t len = e1000e_macreg_read(d, E1000E_TDLEN) / E1000E_TXD_LEN;
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uint32_t len = e1000e_macreg_read(d, E1000E_TDLEN) / E1000_RING_DESC_LEN;
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qtest_memwrite(d_pci->pci_dev.bus->qts, d->tx_ring + tail * E1000E_TXD_LEN,
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descr, E1000E_TXD_LEN);
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qtest_memwrite(d_pci->pci_dev.bus->qts,
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d->tx_ring + tail * E1000_RING_DESC_LEN,
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descr, E1000_RING_DESC_LEN);
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e1000e_macreg_write(d, E1000E_TDT, (tail + 1) % len);
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/* Read WB data for the packet transmitted */
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qtest_memread(d_pci->pci_dev.bus->qts, d->tx_ring + tail * E1000E_TXD_LEN,
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descr, E1000E_TXD_LEN);
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qtest_memread(d_pci->pci_dev.bus->qts,
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d->tx_ring + tail * E1000_RING_DESC_LEN,
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descr, E1000_RING_DESC_LEN);
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}
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void e1000e_rx_ring_push(QE1000E *d, void *descr)
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{
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QE1000E_PCI *d_pci = container_of(d, QE1000E_PCI, e1000e);
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uint32_t tail = e1000e_macreg_read(d, E1000E_RDT);
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uint32_t len = e1000e_macreg_read(d, E1000E_RDLEN) / E1000E_RXD_LEN;
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uint32_t len = e1000e_macreg_read(d, E1000E_RDLEN) / E1000_RING_DESC_LEN;
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qtest_memwrite(d_pci->pci_dev.bus->qts, d->rx_ring + tail * E1000E_RXD_LEN,
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descr, E1000E_RXD_LEN);
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qtest_memwrite(d_pci->pci_dev.bus->qts,
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d->rx_ring + tail * E1000_RING_DESC_LEN,
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descr, E1000_RING_DESC_LEN);
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e1000e_macreg_write(d, E1000E_RDT, (tail + 1) % len);
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/* Read WB data for the packet received */
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qtest_memread(d_pci->pci_dev.bus->qts, d->rx_ring + tail * E1000E_RXD_LEN,
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descr, E1000E_RXD_LEN);
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qtest_memread(d_pci->pci_dev.bus->qts,
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d->rx_ring + tail * E1000_RING_DESC_LEN,
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descr, E1000_RING_DESC_LEN);
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}
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static void e1000e_foreach_callback(QPCIDevice *dev, int devfn, void *data)
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@ -151,53 +120,53 @@ static void e1000e_pci_start_hw(QOSGraphObject *obj)
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qpci_device_enable(&d->pci_dev);
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/* Reset the device */
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val = e1000e_macreg_read(&d->e1000e, E1000E_CTRL);
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e1000e_macreg_write(&d->e1000e, E1000E_CTRL, val | E1000E_CTRL_RESET);
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val = e1000e_macreg_read(&d->e1000e, E1000_CTRL);
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e1000e_macreg_write(&d->e1000e, E1000_CTRL, val | E1000_CTRL_RST);
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/* Enable and configure MSI-X */
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qpci_msix_enable(&d->pci_dev);
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e1000e_macreg_write(&d->e1000e, E1000E_IVAR, E1000E_IVAR_TEST_CFG);
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e1000e_macreg_write(&d->e1000e, E1000_IVAR, E1000E_IVAR_TEST_CFG);
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/* Check the device status - link and speed */
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val = e1000e_macreg_read(&d->e1000e, E1000E_STATUS);
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g_assert_cmphex(val & (E1000E_STATUS_LU | E1000E_STATUS_ASDV1000),
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==, E1000E_STATUS_LU | E1000E_STATUS_ASDV1000);
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val = e1000e_macreg_read(&d->e1000e, E1000_STATUS);
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g_assert_cmphex(val & (E1000_STATUS_LU | E1000_STATUS_LAN_INIT_DONE),
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==, E1000_STATUS_LU | E1000_STATUS_LAN_INIT_DONE);
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/* Initialize TX/RX logic */
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e1000e_macreg_write(&d->e1000e, E1000E_RCTL, 0);
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e1000e_macreg_write(&d->e1000e, E1000E_TCTL, 0);
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e1000e_macreg_write(&d->e1000e, E1000_RCTL, 0);
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e1000e_macreg_write(&d->e1000e, E1000_TCTL, 0);
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/* Notify the device that the driver is ready */
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val = e1000e_macreg_read(&d->e1000e, E1000E_CTRL_EXT);
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e1000e_macreg_write(&d->e1000e, E1000E_CTRL_EXT,
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val | E1000E_CTRL_EXT_DRV_LOAD | E1000E_CTRL_EXT_TXLSFLOW);
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val = e1000e_macreg_read(&d->e1000e, E1000_CTRL_EXT);
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e1000e_macreg_write(&d->e1000e, E1000_CTRL_EXT,
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val | E1000_CTRL_EXT_DRV_LOAD);
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e1000e_macreg_write(&d->e1000e, E1000E_TDBAL,
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e1000e_macreg_write(&d->e1000e, E1000_TDBAL,
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(uint32_t) d->e1000e.tx_ring);
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e1000e_macreg_write(&d->e1000e, E1000E_TDBAH,
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e1000e_macreg_write(&d->e1000e, E1000_TDBAH,
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(uint32_t) (d->e1000e.tx_ring >> 32));
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e1000e_macreg_write(&d->e1000e, E1000E_TDLEN, E1000E_RING_LEN);
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e1000e_macreg_write(&d->e1000e, E1000E_TDT, 0);
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e1000e_macreg_write(&d->e1000e, E1000E_TDH, 0);
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e1000e_macreg_write(&d->e1000e, E1000_TDH, 0);
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/* Enable transmit */
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e1000e_macreg_write(&d->e1000e, E1000E_TCTL, E1000E_TCTL_EN);
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e1000e_macreg_write(&d->e1000e, E1000E_RDBAL,
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e1000e_macreg_write(&d->e1000e, E1000_TCTL, E1000_TCTL_EN);
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e1000e_macreg_write(&d->e1000e, E1000_RDBAL,
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(uint32_t)d->e1000e.rx_ring);
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e1000e_macreg_write(&d->e1000e, E1000E_RDBAH,
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e1000e_macreg_write(&d->e1000e, E1000_RDBAH,
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(uint32_t)(d->e1000e.rx_ring >> 32));
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e1000e_macreg_write(&d->e1000e, E1000E_RDLEN, E1000E_RING_LEN);
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e1000e_macreg_write(&d->e1000e, E1000E_RDT, 0);
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e1000e_macreg_write(&d->e1000e, E1000E_RDH, 0);
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e1000e_macreg_write(&d->e1000e, E1000_RDH, 0);
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/* Enable receive */
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e1000e_macreg_write(&d->e1000e, E1000E_RFCTL, E1000E_RFCTL_EXTEN);
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e1000e_macreg_write(&d->e1000e, E1000E_RCTL, E1000E_RCTL_EN |
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E1000E_RCTL_UPE |
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E1000E_RCTL_MPE);
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e1000e_macreg_write(&d->e1000e, E1000_RFCTL, E1000_RFCTL_EXTEN);
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e1000e_macreg_write(&d->e1000e, E1000_RCTL, E1000_RCTL_EN |
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E1000_RCTL_UPE |
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E1000_RCTL_MPE);
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/* Enable all interrupts */
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e1000e_macreg_write(&d->e1000e, E1000E_IMS, 0xFFFFFFFF);
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e1000e_macreg_write(&d->e1000e, E1000_IMS, 0xFFFFFFFF);
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}
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