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target/riscv: Remove privileged spec version restriction for RVV 

The RVV specification does not require that the core needs to support
the privileged specification v1.12.0 to support RVV, and there is no
dependency from ISA level.

This commit removes the restriction from both RVV CSRs and extension CPU
ISA string.

Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Bin Meng <bmeng@tinylab.org>
Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20230208063209.27279-1-frank.chang@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
This commit is contained in:
Frank Chang 2023-02-08 14:32:08 +08:00 committed by Palmer Dabbelt
parent 8b64475bd5
commit 0e660142ca
No known key found for this signature in database
GPG Key ID: 2E1319F35FBB1889
2 changed files with 8 additions and 15 deletions
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2
target/riscv/cpu.c
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@ -73,7 +73,7 @@ struct isa_ext_data {
*/
static const struct isa_ext_data isa_edata_arr[] = {
ISA_EXT_DATA_ENTRY(h, false, PRIV_VERSION_1_12_0, ext_h),
ISA_EXT_DATA_ENTRY(v, false, PRIV_VERSION_1_12_0, ext_v),
ISA_EXT_DATA_ENTRY(v, false, PRIV_VERSION_1_10_0, ext_v),
ISA_EXT_DATA_ENTRY(zicsr, true, PRIV_VERSION_1_10_0, ext_icsr),
ISA_EXT_DATA_ENTRY(zifencei, true, PRIV_VERSION_1_10_0, ext_ifencei),
ISA_EXT_DATA_ENTRY(zihintpause, true, PRIV_VERSION_1_10_0, ext_zihintpause),

21
target/riscv/csr.c
View File

@ -3980,20 +3980,13 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
[CSR_FRM] = { "frm", fs, read_frm, write_frm },
[CSR_FCSR] = { "fcsr", fs, read_fcsr, write_fcsr },
/* Vector CSRs */
[CSR_VSTART] = { "vstart", vs, read_vstart, write_vstart,
.min_priv_ver = PRIV_VERSION_1_12_0 },
[CSR_VXSAT] = { "vxsat", vs, read_vxsat, write_vxsat,
.min_priv_ver = PRIV_VERSION_1_12_0 },
[CSR_VXRM] = { "vxrm", vs, read_vxrm, write_vxrm,
.min_priv_ver = PRIV_VERSION_1_12_0 },
[CSR_VCSR] = { "vcsr", vs, read_vcsr, write_vcsr,
.min_priv_ver = PRIV_VERSION_1_12_0 },
[CSR_VL] = { "vl", vs, read_vl,
.min_priv_ver = PRIV_VERSION_1_12_0 },
[CSR_VTYPE] = { "vtype", vs, read_vtype,
.min_priv_ver = PRIV_VERSION_1_12_0 },
[CSR_VLENB] = { "vlenb", vs, read_vlenb,
.min_priv_ver = PRIV_VERSION_1_12_0 },
[CSR_VSTART] = { "vstart", vs, read_vstart, write_vstart },
[CSR_VXSAT] = { "vxsat", vs, read_vxsat, write_vxsat },
[CSR_VXRM] = { "vxrm", vs, read_vxrm, write_vxrm },
[CSR_VCSR] = { "vcsr", vs, read_vcsr, write_vcsr },
[CSR_VL] = { "vl", vs, read_vl },
[CSR_VTYPE] = { "vtype", vs, read_vtype },
[CSR_VLENB] = { "vlenb", vs, read_vlenb },
/* User Timers and Counters */
[CSR_CYCLE] = { "cycle", ctr, read_hpmcounter },
[CSR_INSTRET] = { "instret", ctr, read_hpmcounter },