From 0ea00c9a3c5e69ca30007f982fb7f2163ab8116c Mon Sep 17 00:00:00 2001
From: bellard <bellard@c046a42c-6fe2-441c-8c8c-71466251a162>
Date: Sat, 29 Mar 2003 16:47:34 +0000
Subject: [PATCH] added number of arguments

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@52 c046a42c-6fe2-441c-8c8c-71466251a162
---
 dyngen.c   |    9 +-
 opc-i386.h | 1171 ++++++++++++++++++++++++++++------------------------
 2 files changed, 642 insertions(+), 538 deletions(-)

diff --git a/dyngen.c b/dyngen.c
index ed68610639..5cd59cb9df 100644
--- a/dyngen.c
+++ b/dyngen.c
@@ -282,7 +282,9 @@ void gen_code(const char *name, unsigned long offset, unsigned long size,
             error("inconsistent argument numbering in %s", name);
     }
 
-    if (gen_switch) {
+    if (gen_switch == 2) {
+        fprintf(outfile, "DEF(%s, %d)\n", name + 3, nb_args);
+    } else if (gen_switch == 1) {
 
         /* output C code */
         fprintf(outfile, "case INDEX_%s: {\n", name);
@@ -559,12 +561,13 @@ int load_elf(const char *filename, FILE *outfile, int do_print_enum)
     }
 
     if (do_print_enum) {
-        fprintf(outfile, "DEF(end)\n");
+        fprintf(outfile, "DEF(end, 0)\n");
         for(i = 0, sym = symtab; i < nb_syms; i++, sym++) {
             const char *name, *p;
             name = strtab + sym->st_name;
             if (strstart(name, OP_PREFIX, &p)) {
-                fprintf(outfile, "DEF(%s)\n", p);
+                gen_code(name, sym->st_value, sym->st_size, outfile, 
+                         text, relocs, nb_relocs, reloc_sh_type, symtab, strtab, 2);
             }
         }
     } else {
diff --git a/opc-i386.h b/opc-i386.h
index eceecf41b8..2a50e26a75 100644
--- a/opc-i386.h
+++ b/opc-i386.h
@@ -1,535 +1,636 @@
-DEF(end)
-DEF(movl_A0_EAX)
-DEF(addl_A0_EAX)
-DEF(addl_A0_EAX_s1)
-DEF(addl_A0_EAX_s2)
-DEF(addl_A0_EAX_s3)
-DEF(movl_T0_EAX)
-DEF(movl_T1_EAX)
-DEF(movh_T0_EAX)
-DEF(movh_T1_EAX)
-DEF(movl_EAX_T0)
-DEF(movl_EAX_T1)
-DEF(movl_EAX_A0)
-DEF(cmovw_EAX_T1_T0)
-DEF(cmovl_EAX_T1_T0)
-DEF(movw_EAX_T0)
-DEF(movw_EAX_T1)
-DEF(movw_EAX_A0)
-DEF(movb_EAX_T0)
-DEF(movh_EAX_T0)
-DEF(movb_EAX_T1)
-DEF(movh_EAX_T1)
-DEF(movl_A0_ECX)
-DEF(addl_A0_ECX)
-DEF(addl_A0_ECX_s1)
-DEF(addl_A0_ECX_s2)
-DEF(addl_A0_ECX_s3)
-DEF(movl_T0_ECX)
-DEF(movl_T1_ECX)
-DEF(movh_T0_ECX)
-DEF(movh_T1_ECX)
-DEF(movl_ECX_T0)
-DEF(movl_ECX_T1)
-DEF(movl_ECX_A0)
-DEF(cmovw_ECX_T1_T0)
-DEF(cmovl_ECX_T1_T0)
-DEF(movw_ECX_T0)
-DEF(movw_ECX_T1)
-DEF(movw_ECX_A0)
-DEF(movb_ECX_T0)
-DEF(movh_ECX_T0)
-DEF(movb_ECX_T1)
-DEF(movh_ECX_T1)
-DEF(movl_A0_EDX)
-DEF(addl_A0_EDX)
-DEF(addl_A0_EDX_s1)
-DEF(addl_A0_EDX_s2)
-DEF(addl_A0_EDX_s3)
-DEF(movl_T0_EDX)
-DEF(movl_T1_EDX)
-DEF(movh_T0_EDX)
-DEF(movh_T1_EDX)
-DEF(movl_EDX_T0)
-DEF(movl_EDX_T1)
-DEF(movl_EDX_A0)
-DEF(cmovw_EDX_T1_T0)
-DEF(cmovl_EDX_T1_T0)
-DEF(movw_EDX_T0)
-DEF(movw_EDX_T1)
-DEF(movw_EDX_A0)
-DEF(movb_EDX_T0)
-DEF(movh_EDX_T0)
-DEF(movb_EDX_T1)
-DEF(movh_EDX_T1)
-DEF(movl_A0_EBX)
-DEF(addl_A0_EBX)
-DEF(addl_A0_EBX_s1)
-DEF(addl_A0_EBX_s2)
-DEF(addl_A0_EBX_s3)
-DEF(movl_T0_EBX)
-DEF(movl_T1_EBX)
-DEF(movh_T0_EBX)
-DEF(movh_T1_EBX)
-DEF(movl_EBX_T0)
-DEF(movl_EBX_T1)
-DEF(movl_EBX_A0)
-DEF(cmovw_EBX_T1_T0)
-DEF(cmovl_EBX_T1_T0)
-DEF(movw_EBX_T0)
-DEF(movw_EBX_T1)
-DEF(movw_EBX_A0)
-DEF(movb_EBX_T0)
-DEF(movh_EBX_T0)
-DEF(movb_EBX_T1)
-DEF(movh_EBX_T1)
-DEF(movl_A0_ESP)
-DEF(addl_A0_ESP)
-DEF(addl_A0_ESP_s1)
-DEF(addl_A0_ESP_s2)
-DEF(addl_A0_ESP_s3)
-DEF(movl_T0_ESP)
-DEF(movl_T1_ESP)
-DEF(movh_T0_ESP)
-DEF(movh_T1_ESP)
-DEF(movl_ESP_T0)
-DEF(movl_ESP_T1)
-DEF(movl_ESP_A0)
-DEF(cmovw_ESP_T1_T0)
-DEF(cmovl_ESP_T1_T0)
-DEF(movw_ESP_T0)
-DEF(movw_ESP_T1)
-DEF(movw_ESP_A0)
-DEF(movb_ESP_T0)
-DEF(movh_ESP_T0)
-DEF(movb_ESP_T1)
-DEF(movh_ESP_T1)
-DEF(movl_A0_EBP)
-DEF(addl_A0_EBP)
-DEF(addl_A0_EBP_s1)
-DEF(addl_A0_EBP_s2)
-DEF(addl_A0_EBP_s3)
-DEF(movl_T0_EBP)
-DEF(movl_T1_EBP)
-DEF(movh_T0_EBP)
-DEF(movh_T1_EBP)
-DEF(movl_EBP_T0)
-DEF(movl_EBP_T1)
-DEF(movl_EBP_A0)
-DEF(cmovw_EBP_T1_T0)
-DEF(cmovl_EBP_T1_T0)
-DEF(movw_EBP_T0)
-DEF(movw_EBP_T1)
-DEF(movw_EBP_A0)
-DEF(movb_EBP_T0)
-DEF(movh_EBP_T0)
-DEF(movb_EBP_T1)
-DEF(movh_EBP_T1)
-DEF(movl_A0_ESI)
-DEF(addl_A0_ESI)
-DEF(addl_A0_ESI_s1)
-DEF(addl_A0_ESI_s2)
-DEF(addl_A0_ESI_s3)
-DEF(movl_T0_ESI)
-DEF(movl_T1_ESI)
-DEF(movh_T0_ESI)
-DEF(movh_T1_ESI)
-DEF(movl_ESI_T0)
-DEF(movl_ESI_T1)
-DEF(movl_ESI_A0)
-DEF(cmovw_ESI_T1_T0)
-DEF(cmovl_ESI_T1_T0)
-DEF(movw_ESI_T0)
-DEF(movw_ESI_T1)
-DEF(movw_ESI_A0)
-DEF(movb_ESI_T0)
-DEF(movh_ESI_T0)
-DEF(movb_ESI_T1)
-DEF(movh_ESI_T1)
-DEF(movl_A0_EDI)
-DEF(addl_A0_EDI)
-DEF(addl_A0_EDI_s1)
-DEF(addl_A0_EDI_s2)
-DEF(addl_A0_EDI_s3)
-DEF(movl_T0_EDI)
-DEF(movl_T1_EDI)
-DEF(movh_T0_EDI)
-DEF(movh_T1_EDI)
-DEF(movl_EDI_T0)
-DEF(movl_EDI_T1)
-DEF(movl_EDI_A0)
-DEF(cmovw_EDI_T1_T0)
-DEF(cmovl_EDI_T1_T0)
-DEF(movw_EDI_T0)
-DEF(movw_EDI_T1)
-DEF(movw_EDI_A0)
-DEF(movb_EDI_T0)
-DEF(movh_EDI_T0)
-DEF(movb_EDI_T1)
-DEF(movh_EDI_T1)
-DEF(addl_T0_T1_cc)
-DEF(orl_T0_T1_cc)
-DEF(andl_T0_T1_cc)
-DEF(subl_T0_T1_cc)
-DEF(xorl_T0_T1_cc)
-DEF(cmpl_T0_T1_cc)
-DEF(negl_T0_cc)
-DEF(incl_T0_cc)
-DEF(decl_T0_cc)
-DEF(testl_T0_T1_cc)
-DEF(addl_T0_T1)
-DEF(orl_T0_T1)
-DEF(andl_T0_T1)
-DEF(subl_T0_T1)
-DEF(xorl_T0_T1)
-DEF(negl_T0)
-DEF(incl_T0)
-DEF(decl_T0)
-DEF(notl_T0)
-DEF(bswapl_T0)
-DEF(mulb_AL_T0)
-DEF(imulb_AL_T0)
-DEF(mulw_AX_T0)
-DEF(imulw_AX_T0)
-DEF(mull_EAX_T0)
-DEF(imull_EAX_T0)
-DEF(imulw_T0_T1)
-DEF(imull_T0_T1)
-DEF(divb_AL_T0)
-DEF(idivb_AL_T0)
-DEF(divw_AX_T0)
-DEF(idivw_AX_T0)
-DEF(divl_EAX_T0)
-DEF(idivl_EAX_T0)
-DEF(movl_T0_im)
-DEF(addl_T0_im)
-DEF(andl_T0_ffff)
-DEF(movl_T0_T1)
-DEF(movl_T1_im)
-DEF(addl_T1_im)
-DEF(movl_T1_A0)
-DEF(movl_A0_im)
-DEF(addl_A0_im)
-DEF(addl_A0_AL)
-DEF(andl_A0_ffff)
-DEF(ldub_T0_A0)
-DEF(ldsb_T0_A0)
-DEF(lduw_T0_A0)
-DEF(ldsw_T0_A0)
-DEF(ldl_T0_A0)
-DEF(ldub_T1_A0)
-DEF(ldsb_T1_A0)
-DEF(lduw_T1_A0)
-DEF(ldsw_T1_A0)
-DEF(ldl_T1_A0)
-DEF(stb_T0_A0)
-DEF(stw_T0_A0)
-DEF(stl_T0_A0)
-DEF(add_bitw_A0_T1)
-DEF(add_bitl_A0_T1)
-DEF(jmp_T0)
-DEF(jmp_im)
-DEF(int_im)
-DEF(int3)
-DEF(into)
-DEF(jb_subb)
-DEF(jz_subb)
-DEF(jbe_subb)
-DEF(js_subb)
-DEF(jl_subb)
-DEF(jle_subb)
-DEF(setb_T0_subb)
-DEF(setz_T0_subb)
-DEF(setbe_T0_subb)
-DEF(sets_T0_subb)
-DEF(setl_T0_subb)
-DEF(setle_T0_subb)
-DEF(rolb_T0_T1_cc)
-DEF(rolb_T0_T1)
-DEF(rorb_T0_T1_cc)
-DEF(rorb_T0_T1)
-DEF(rclb_T0_T1_cc)
-DEF(rcrb_T0_T1_cc)
-DEF(shlb_T0_T1_cc)
-DEF(shlb_T0_T1)
-DEF(shrb_T0_T1_cc)
-DEF(shrb_T0_T1)
-DEF(sarb_T0_T1_cc)
-DEF(sarb_T0_T1)
-DEF(adcb_T0_T1_cc)
-DEF(sbbb_T0_T1_cc)
-DEF(cmpxchgb_T0_T1_EAX_cc)
-DEF(movsb)
-DEF(rep_movsb)
-DEF(stosb)
-DEF(rep_stosb)
-DEF(lodsb)
-DEF(rep_lodsb)
-DEF(scasb)
-DEF(repz_scasb)
-DEF(repnz_scasb)
-DEF(cmpsb)
-DEF(repz_cmpsb)
-DEF(repnz_cmpsb)
-DEF(outsb)
-DEF(rep_outsb)
-DEF(insb)
-DEF(rep_insb)
-DEF(outb_T0_T1)
-DEF(inb_T0_T1)
-DEF(jb_subw)
-DEF(jz_subw)
-DEF(jbe_subw)
-DEF(js_subw)
-DEF(jl_subw)
-DEF(jle_subw)
-DEF(loopnzw)
-DEF(loopzw)
-DEF(loopw)
-DEF(jecxzw)
-DEF(setb_T0_subw)
-DEF(setz_T0_subw)
-DEF(setbe_T0_subw)
-DEF(sets_T0_subw)
-DEF(setl_T0_subw)
-DEF(setle_T0_subw)
-DEF(rolw_T0_T1_cc)
-DEF(rolw_T0_T1)
-DEF(rorw_T0_T1_cc)
-DEF(rorw_T0_T1)
-DEF(rclw_T0_T1_cc)
-DEF(rcrw_T0_T1_cc)
-DEF(shlw_T0_T1_cc)
-DEF(shlw_T0_T1)
-DEF(shrw_T0_T1_cc)
-DEF(shrw_T0_T1)
-DEF(sarw_T0_T1_cc)
-DEF(sarw_T0_T1)
-DEF(shldw_T0_T1_im_cc)
-DEF(shldw_T0_T1_ECX_cc)
-DEF(shrdw_T0_T1_im_cc)
-DEF(shrdw_T0_T1_ECX_cc)
-DEF(adcw_T0_T1_cc)
-DEF(sbbw_T0_T1_cc)
-DEF(cmpxchgw_T0_T1_EAX_cc)
-DEF(btw_T0_T1_cc)
-DEF(btsw_T0_T1_cc)
-DEF(btrw_T0_T1_cc)
-DEF(btcw_T0_T1_cc)
-DEF(bsfw_T0_cc)
-DEF(bsrw_T0_cc)
-DEF(movsw)
-DEF(rep_movsw)
-DEF(stosw)
-DEF(rep_stosw)
-DEF(lodsw)
-DEF(rep_lodsw)
-DEF(scasw)
-DEF(repz_scasw)
-DEF(repnz_scasw)
-DEF(cmpsw)
-DEF(repz_cmpsw)
-DEF(repnz_cmpsw)
-DEF(outsw)
-DEF(rep_outsw)
-DEF(insw)
-DEF(rep_insw)
-DEF(outw_T0_T1)
-DEF(inw_T0_T1)
-DEF(jb_subl)
-DEF(jz_subl)
-DEF(jbe_subl)
-DEF(js_subl)
-DEF(jl_subl)
-DEF(jle_subl)
-DEF(loopnzl)
-DEF(loopzl)
-DEF(loopl)
-DEF(jecxzl)
-DEF(setb_T0_subl)
-DEF(setz_T0_subl)
-DEF(setbe_T0_subl)
-DEF(sets_T0_subl)
-DEF(setl_T0_subl)
-DEF(setle_T0_subl)
-DEF(roll_T0_T1_cc)
-DEF(roll_T0_T1)
-DEF(rorl_T0_T1_cc)
-DEF(rorl_T0_T1)
-DEF(rcll_T0_T1_cc)
-DEF(rcrl_T0_T1_cc)
-DEF(shll_T0_T1_cc)
-DEF(shll_T0_T1)
-DEF(shrl_T0_T1_cc)
-DEF(shrl_T0_T1)
-DEF(sarl_T0_T1_cc)
-DEF(sarl_T0_T1)
-DEF(shldl_T0_T1_im_cc)
-DEF(shldl_T0_T1_ECX_cc)
-DEF(shrdl_T0_T1_im_cc)
-DEF(shrdl_T0_T1_ECX_cc)
-DEF(adcl_T0_T1_cc)
-DEF(sbbl_T0_T1_cc)
-DEF(cmpxchgl_T0_T1_EAX_cc)
-DEF(btl_T0_T1_cc)
-DEF(btsl_T0_T1_cc)
-DEF(btrl_T0_T1_cc)
-DEF(btcl_T0_T1_cc)
-DEF(bsfl_T0_cc)
-DEF(bsrl_T0_cc)
-DEF(movsl)
-DEF(rep_movsl)
-DEF(stosl)
-DEF(rep_stosl)
-DEF(lodsl)
-DEF(rep_lodsl)
-DEF(scasl)
-DEF(repz_scasl)
-DEF(repnz_scasl)
-DEF(cmpsl)
-DEF(repz_cmpsl)
-DEF(repnz_cmpsl)
-DEF(outsl)
-DEF(rep_outsl)
-DEF(insl)
-DEF(rep_insl)
-DEF(outl_T0_T1)
-DEF(inl_T0_T1)
-DEF(movsbl_T0_T0)
-DEF(movzbl_T0_T0)
-DEF(movswl_T0_T0)
-DEF(movzwl_T0_T0)
-DEF(movswl_EAX_AX)
-DEF(movsbw_AX_AL)
-DEF(movslq_EDX_EAX)
-DEF(movswl_DX_AX)
-DEF(pushl_T0)
-DEF(pushw_T0)
-DEF(pushl_ss32_T0)
-DEF(pushw_ss32_T0)
-DEF(pushl_ss16_T0)
-DEF(pushw_ss16_T0)
-DEF(popl_T0)
-DEF(popw_T0)
-DEF(popl_ss32_T0)
-DEF(popw_ss32_T0)
-DEF(popl_ss16_T0)
-DEF(popw_ss16_T0)
-DEF(addl_ESP_4)
-DEF(addl_ESP_2)
-DEF(addw_ESP_4)
-DEF(addw_ESP_2)
-DEF(addl_ESP_im)
-DEF(addw_ESP_im)
-DEF(rdtsc)
-DEF(aam)
-DEF(aad)
-DEF(aaa)
-DEF(aas)
-DEF(daa)
-DEF(das)
-DEF(movl_seg_T0)
-DEF(movl_T0_seg)
-DEF(addl_A0_seg)
-DEF(jo_cc)
-DEF(jb_cc)
-DEF(jz_cc)
-DEF(jbe_cc)
-DEF(js_cc)
-DEF(jp_cc)
-DEF(jl_cc)
-DEF(jle_cc)
-DEF(seto_T0_cc)
-DEF(setb_T0_cc)
-DEF(setz_T0_cc)
-DEF(setbe_T0_cc)
-DEF(sets_T0_cc)
-DEF(setp_T0_cc)
-DEF(setl_T0_cc)
-DEF(setle_T0_cc)
-DEF(xor_T0_1)
-DEF(set_cc_op)
-DEF(movl_eflags_T0)
-DEF(movb_eflags_T0)
-DEF(movl_T0_eflags)
-DEF(cld)
-DEF(std)
-DEF(clc)
-DEF(stc)
-DEF(cmc)
-DEF(salc)
-DEF(flds_FT0_A0)
-DEF(fldl_FT0_A0)
-DEF(fild_FT0_A0)
-DEF(fildl_FT0_A0)
-DEF(fildll_FT0_A0)
-DEF(flds_ST0_A0)
-DEF(fldl_ST0_A0)
-DEF(fldt_ST0_A0)
-DEF(fild_ST0_A0)
-DEF(fildl_ST0_A0)
-DEF(fildll_ST0_A0)
-DEF(fsts_ST0_A0)
-DEF(fstl_ST0_A0)
-DEF(fstt_ST0_A0)
-DEF(fist_ST0_A0)
-DEF(fistl_ST0_A0)
-DEF(fistll_ST0_A0)
-DEF(fbld_ST0_A0)
-DEF(fbst_ST0_A0)
-DEF(fpush)
-DEF(fpop)
-DEF(fdecstp)
-DEF(fincstp)
-DEF(fmov_ST0_FT0)
-DEF(fmov_FT0_STN)
-DEF(fmov_ST0_STN)
-DEF(fmov_STN_ST0)
-DEF(fxchg_ST0_STN)
-DEF(fcom_ST0_FT0)
-DEF(fucom_ST0_FT0)
-DEF(fadd_ST0_FT0)
-DEF(fmul_ST0_FT0)
-DEF(fsub_ST0_FT0)
-DEF(fsubr_ST0_FT0)
-DEF(fdiv_ST0_FT0)
-DEF(fdivr_ST0_FT0)
-DEF(fadd_STN_ST0)
-DEF(fmul_STN_ST0)
-DEF(fsub_STN_ST0)
-DEF(fsubr_STN_ST0)
-DEF(fdiv_STN_ST0)
-DEF(fdivr_STN_ST0)
-DEF(fchs_ST0)
-DEF(fabs_ST0)
-DEF(fxam_ST0)
-DEF(fld1_ST0)
-DEF(fldl2t_ST0)
-DEF(fldl2e_ST0)
-DEF(fldpi_ST0)
-DEF(fldlg2_ST0)
-DEF(fldln2_ST0)
-DEF(fldz_ST0)
-DEF(fldz_FT0)
-DEF(f2xm1)
-DEF(fyl2x)
-DEF(fptan)
-DEF(fpatan)
-DEF(fxtract)
-DEF(fprem1)
-DEF(fprem)
-DEF(fyl2xp1)
-DEF(fsqrt)
-DEF(fsincos)
-DEF(frndint)
-DEF(fscale)
-DEF(fsin)
-DEF(fcos)
-DEF(fnstsw_A0)
-DEF(fnstsw_EAX)
-DEF(fnstcw_A0)
-DEF(fldcw_A0)
-DEF(fclex)
-DEF(fninit)
-DEF(lock)
-DEF(unlock)
+DEF(end, 0)
+DEF(movl_A0_EAX, 0)
+DEF(addl_A0_EAX, 0)
+DEF(addl_A0_EAX_s1, 0)
+DEF(addl_A0_EAX_s2, 0)
+DEF(addl_A0_EAX_s3, 0)
+DEF(movl_T0_EAX, 0)
+DEF(movl_T1_EAX, 0)
+DEF(movh_T0_EAX, 0)
+DEF(movh_T1_EAX, 0)
+DEF(movl_EAX_T0, 0)
+DEF(movl_EAX_T1, 0)
+DEF(movl_EAX_A0, 0)
+DEF(cmovw_EAX_T1_T0, 0)
+DEF(cmovl_EAX_T1_T0, 0)
+DEF(movw_EAX_T0, 0)
+DEF(movw_EAX_T1, 0)
+DEF(movw_EAX_A0, 0)
+DEF(movb_EAX_T0, 0)
+DEF(movh_EAX_T0, 0)
+DEF(movb_EAX_T1, 0)
+DEF(movh_EAX_T1, 0)
+DEF(movl_A0_ECX, 0)
+DEF(addl_A0_ECX, 0)
+DEF(addl_A0_ECX_s1, 0)
+DEF(addl_A0_ECX_s2, 0)
+DEF(addl_A0_ECX_s3, 0)
+DEF(movl_T0_ECX, 0)
+DEF(movl_T1_ECX, 0)
+DEF(movh_T0_ECX, 0)
+DEF(movh_T1_ECX, 0)
+DEF(movl_ECX_T0, 0)
+DEF(movl_ECX_T1, 0)
+DEF(movl_ECX_A0, 0)
+DEF(cmovw_ECX_T1_T0, 0)
+DEF(cmovl_ECX_T1_T0, 0)
+DEF(movw_ECX_T0, 0)
+DEF(movw_ECX_T1, 0)
+DEF(movw_ECX_A0, 0)
+DEF(movb_ECX_T0, 0)
+DEF(movh_ECX_T0, 0)
+DEF(movb_ECX_T1, 0)
+DEF(movh_ECX_T1, 0)
+DEF(movl_A0_EDX, 0)
+DEF(addl_A0_EDX, 0)
+DEF(addl_A0_EDX_s1, 0)
+DEF(addl_A0_EDX_s2, 0)
+DEF(addl_A0_EDX_s3, 0)
+DEF(movl_T0_EDX, 0)
+DEF(movl_T1_EDX, 0)
+DEF(movh_T0_EDX, 0)
+DEF(movh_T1_EDX, 0)
+DEF(movl_EDX_T0, 0)
+DEF(movl_EDX_T1, 0)
+DEF(movl_EDX_A0, 0)
+DEF(cmovw_EDX_T1_T0, 0)
+DEF(cmovl_EDX_T1_T0, 0)
+DEF(movw_EDX_T0, 0)
+DEF(movw_EDX_T1, 0)
+DEF(movw_EDX_A0, 0)
+DEF(movb_EDX_T0, 0)
+DEF(movh_EDX_T0, 0)
+DEF(movb_EDX_T1, 0)
+DEF(movh_EDX_T1, 0)
+DEF(movl_A0_EBX, 0)
+DEF(addl_A0_EBX, 0)
+DEF(addl_A0_EBX_s1, 0)
+DEF(addl_A0_EBX_s2, 0)
+DEF(addl_A0_EBX_s3, 0)
+DEF(movl_T0_EBX, 0)
+DEF(movl_T1_EBX, 0)
+DEF(movh_T0_EBX, 0)
+DEF(movh_T1_EBX, 0)
+DEF(movl_EBX_T0, 0)
+DEF(movl_EBX_T1, 0)
+DEF(movl_EBX_A0, 0)
+DEF(cmovw_EBX_T1_T0, 0)
+DEF(cmovl_EBX_T1_T0, 0)
+DEF(movw_EBX_T0, 0)
+DEF(movw_EBX_T1, 0)
+DEF(movw_EBX_A0, 0)
+DEF(movb_EBX_T0, 0)
+DEF(movh_EBX_T0, 0)
+DEF(movb_EBX_T1, 0)
+DEF(movh_EBX_T1, 0)
+DEF(movl_A0_ESP, 0)
+DEF(addl_A0_ESP, 0)
+DEF(addl_A0_ESP_s1, 0)
+DEF(addl_A0_ESP_s2, 0)
+DEF(addl_A0_ESP_s3, 0)
+DEF(movl_T0_ESP, 0)
+DEF(movl_T1_ESP, 0)
+DEF(movh_T0_ESP, 0)
+DEF(movh_T1_ESP, 0)
+DEF(movl_ESP_T0, 0)
+DEF(movl_ESP_T1, 0)
+DEF(movl_ESP_A0, 0)
+DEF(cmovw_ESP_T1_T0, 0)
+DEF(cmovl_ESP_T1_T0, 0)
+DEF(movw_ESP_T0, 0)
+DEF(movw_ESP_T1, 0)
+DEF(movw_ESP_A0, 0)
+DEF(movb_ESP_T0, 0)
+DEF(movh_ESP_T0, 0)
+DEF(movb_ESP_T1, 0)
+DEF(movh_ESP_T1, 0)
+DEF(movl_A0_EBP, 0)
+DEF(addl_A0_EBP, 0)
+DEF(addl_A0_EBP_s1, 0)
+DEF(addl_A0_EBP_s2, 0)
+DEF(addl_A0_EBP_s3, 0)
+DEF(movl_T0_EBP, 0)
+DEF(movl_T1_EBP, 0)
+DEF(movh_T0_EBP, 0)
+DEF(movh_T1_EBP, 0)
+DEF(movl_EBP_T0, 0)
+DEF(movl_EBP_T1, 0)
+DEF(movl_EBP_A0, 0)
+DEF(cmovw_EBP_T1_T0, 0)
+DEF(cmovl_EBP_T1_T0, 0)
+DEF(movw_EBP_T0, 0)
+DEF(movw_EBP_T1, 0)
+DEF(movw_EBP_A0, 0)
+DEF(movb_EBP_T0, 0)
+DEF(movh_EBP_T0, 0)
+DEF(movb_EBP_T1, 0)
+DEF(movh_EBP_T1, 0)
+DEF(movl_A0_ESI, 0)
+DEF(addl_A0_ESI, 0)
+DEF(addl_A0_ESI_s1, 0)
+DEF(addl_A0_ESI_s2, 0)
+DEF(addl_A0_ESI_s3, 0)
+DEF(movl_T0_ESI, 0)
+DEF(movl_T1_ESI, 0)
+DEF(movh_T0_ESI, 0)
+DEF(movh_T1_ESI, 0)
+DEF(movl_ESI_T0, 0)
+DEF(movl_ESI_T1, 0)
+DEF(movl_ESI_A0, 0)
+DEF(cmovw_ESI_T1_T0, 0)
+DEF(cmovl_ESI_T1_T0, 0)
+DEF(movw_ESI_T0, 0)
+DEF(movw_ESI_T1, 0)
+DEF(movw_ESI_A0, 0)
+DEF(movb_ESI_T0, 0)
+DEF(movh_ESI_T0, 0)
+DEF(movb_ESI_T1, 0)
+DEF(movh_ESI_T1, 0)
+DEF(movl_A0_EDI, 0)
+DEF(addl_A0_EDI, 0)
+DEF(addl_A0_EDI_s1, 0)
+DEF(addl_A0_EDI_s2, 0)
+DEF(addl_A0_EDI_s3, 0)
+DEF(movl_T0_EDI, 0)
+DEF(movl_T1_EDI, 0)
+DEF(movh_T0_EDI, 0)
+DEF(movh_T1_EDI, 0)
+DEF(movl_EDI_T0, 0)
+DEF(movl_EDI_T1, 0)
+DEF(movl_EDI_A0, 0)
+DEF(cmovw_EDI_T1_T0, 0)
+DEF(cmovl_EDI_T1_T0, 0)
+DEF(movw_EDI_T0, 0)
+DEF(movw_EDI_T1, 0)
+DEF(movw_EDI_A0, 0)
+DEF(movb_EDI_T0, 0)
+DEF(movh_EDI_T0, 0)
+DEF(movb_EDI_T1, 0)
+DEF(movh_EDI_T1, 0)
+DEF(addl_T0_T1_cc, 0)
+DEF(orl_T0_T1_cc, 0)
+DEF(andl_T0_T1_cc, 0)
+DEF(subl_T0_T1_cc, 0)
+DEF(xorl_T0_T1_cc, 0)
+DEF(cmpl_T0_T1_cc, 0)
+DEF(negl_T0_cc, 0)
+DEF(incl_T0_cc, 0)
+DEF(decl_T0_cc, 0)
+DEF(testl_T0_T1_cc, 0)
+DEF(addl_T0_T1, 0)
+DEF(orl_T0_T1, 0)
+DEF(andl_T0_T1, 0)
+DEF(subl_T0_T1, 0)
+DEF(xorl_T0_T1, 0)
+DEF(negl_T0, 0)
+DEF(incl_T0, 0)
+DEF(decl_T0, 0)
+DEF(notl_T0, 0)
+DEF(bswapl_T0, 0)
+DEF(mulb_AL_T0, 0)
+DEF(imulb_AL_T0, 0)
+DEF(mulw_AX_T0, 0)
+DEF(imulw_AX_T0, 0)
+DEF(mull_EAX_T0, 0)
+DEF(imull_EAX_T0, 0)
+DEF(imulw_T0_T1, 0)
+DEF(imull_T0_T1, 0)
+DEF(divb_AL_T0, 0)
+DEF(idivb_AL_T0, 0)
+DEF(divw_AX_T0, 0)
+DEF(idivw_AX_T0, 0)
+DEF(divl_EAX_T0, 0)
+DEF(idivl_EAX_T0, 0)
+DEF(movl_T0_im, 1)
+DEF(addl_T0_im, 1)
+DEF(andl_T0_ffff, 0)
+DEF(movl_T0_T1, 0)
+DEF(movl_T1_im, 1)
+DEF(addl_T1_im, 1)
+DEF(movl_T1_A0, 0)
+DEF(movl_A0_im, 1)
+DEF(addl_A0_im, 1)
+DEF(addl_A0_AL, 0)
+DEF(andl_A0_ffff, 0)
+DEF(ldub_T0_A0, 0)
+DEF(ldsb_T0_A0, 0)
+DEF(lduw_T0_A0, 0)
+DEF(ldsw_T0_A0, 0)
+DEF(ldl_T0_A0, 0)
+DEF(ldub_T1_A0, 0)
+DEF(ldsb_T1_A0, 0)
+DEF(lduw_T1_A0, 0)
+DEF(ldsw_T1_A0, 0)
+DEF(ldl_T1_A0, 0)
+DEF(stb_T0_A0, 0)
+DEF(stw_T0_A0, 0)
+DEF(stl_T0_A0, 0)
+DEF(add_bitw_A0_T1, 0)
+DEF(add_bitl_A0_T1, 0)
+DEF(jmp_T0, 0)
+DEF(jmp_im, 1)
+DEF(int_im, 1)
+DEF(int3, 1)
+DEF(into, 0)
+DEF(boundw, 0)
+DEF(boundl, 0)
+DEF(cmpxchg8b, 0)
+DEF(jb_subb, 2)
+DEF(jz_subb, 2)
+DEF(jbe_subb, 2)
+DEF(js_subb, 2)
+DEF(jl_subb, 2)
+DEF(jle_subb, 2)
+DEF(setb_T0_subb, 0)
+DEF(setz_T0_subb, 0)
+DEF(setbe_T0_subb, 0)
+DEF(sets_T0_subb, 0)
+DEF(setl_T0_subb, 0)
+DEF(setle_T0_subb, 0)
+DEF(rolb_T0_T1_cc, 0)
+DEF(rolb_T0_T1, 0)
+DEF(rorb_T0_T1_cc, 0)
+DEF(rorb_T0_T1, 0)
+DEF(rclb_T0_T1_cc, 0)
+DEF(rcrb_T0_T1_cc, 0)
+DEF(shlb_T0_T1_cc, 0)
+DEF(shlb_T0_T1, 0)
+DEF(shrb_T0_T1_cc, 0)
+DEF(shrb_T0_T1, 0)
+DEF(sarb_T0_T1_cc, 0)
+DEF(sarb_T0_T1, 0)
+DEF(adcb_T0_T1_cc, 0)
+DEF(sbbb_T0_T1_cc, 0)
+DEF(cmpxchgb_T0_T1_EAX_cc, 0)
+DEF(movsb_fast, 0)
+DEF(rep_movsb_fast, 0)
+DEF(stosb_fast, 0)
+DEF(rep_stosb_fast, 0)
+DEF(lodsb_fast, 0)
+DEF(rep_lodsb_fast, 0)
+DEF(scasb_fast, 0)
+DEF(repz_scasb_fast, 0)
+DEF(repnz_scasb_fast, 0)
+DEF(cmpsb_fast, 0)
+DEF(repz_cmpsb_fast, 0)
+DEF(repnz_cmpsb_fast, 0)
+DEF(outsb_fast, 0)
+DEF(rep_outsb_fast, 0)
+DEF(insb_fast, 0)
+DEF(rep_insb_fast, 0)
+DEF(movsb_a32, 0)
+DEF(rep_movsb_a32, 0)
+DEF(stosb_a32, 0)
+DEF(rep_stosb_a32, 0)
+DEF(lodsb_a32, 0)
+DEF(rep_lodsb_a32, 0)
+DEF(scasb_a32, 0)
+DEF(repz_scasb_a32, 0)
+DEF(repnz_scasb_a32, 0)
+DEF(cmpsb_a32, 0)
+DEF(repz_cmpsb_a32, 0)
+DEF(repnz_cmpsb_a32, 0)
+DEF(outsb_a32, 0)
+DEF(rep_outsb_a32, 0)
+DEF(insb_a32, 0)
+DEF(rep_insb_a32, 0)
+DEF(movsb_a16, 0)
+DEF(rep_movsb_a16, 0)
+DEF(stosb_a16, 0)
+DEF(rep_stosb_a16, 0)
+DEF(lodsb_a16, 0)
+DEF(rep_lodsb_a16, 0)
+DEF(scasb_a16, 0)
+DEF(repz_scasb_a16, 0)
+DEF(repnz_scasb_a16, 0)
+DEF(cmpsb_a16, 0)
+DEF(repz_cmpsb_a16, 0)
+DEF(repnz_cmpsb_a16, 0)
+DEF(outsb_a16, 0)
+DEF(rep_outsb_a16, 0)
+DEF(insb_a16, 0)
+DEF(rep_insb_a16, 0)
+DEF(outb_T0_T1, 0)
+DEF(inb_T0_T1, 0)
+DEF(jb_subw, 2)
+DEF(jz_subw, 2)
+DEF(jbe_subw, 2)
+DEF(js_subw, 2)
+DEF(jl_subw, 2)
+DEF(jle_subw, 2)
+DEF(loopnzw, 2)
+DEF(loopzw, 2)
+DEF(loopw, 2)
+DEF(jecxzw, 2)
+DEF(setb_T0_subw, 0)
+DEF(setz_T0_subw, 0)
+DEF(setbe_T0_subw, 0)
+DEF(sets_T0_subw, 0)
+DEF(setl_T0_subw, 0)
+DEF(setle_T0_subw, 0)
+DEF(rolw_T0_T1_cc, 0)
+DEF(rolw_T0_T1, 0)
+DEF(rorw_T0_T1_cc, 0)
+DEF(rorw_T0_T1, 0)
+DEF(rclw_T0_T1_cc, 0)
+DEF(rcrw_T0_T1_cc, 0)
+DEF(shlw_T0_T1_cc, 0)
+DEF(shlw_T0_T1, 0)
+DEF(shrw_T0_T1_cc, 0)
+DEF(shrw_T0_T1, 0)
+DEF(sarw_T0_T1_cc, 0)
+DEF(sarw_T0_T1, 0)
+DEF(shldw_T0_T1_im_cc, 1)
+DEF(shldw_T0_T1_ECX_cc, 0)
+DEF(shrdw_T0_T1_im_cc, 1)
+DEF(shrdw_T0_T1_ECX_cc, 0)
+DEF(adcw_T0_T1_cc, 0)
+DEF(sbbw_T0_T1_cc, 0)
+DEF(cmpxchgw_T0_T1_EAX_cc, 0)
+DEF(btw_T0_T1_cc, 0)
+DEF(btsw_T0_T1_cc, 0)
+DEF(btrw_T0_T1_cc, 0)
+DEF(btcw_T0_T1_cc, 0)
+DEF(bsfw_T0_cc, 0)
+DEF(bsrw_T0_cc, 0)
+DEF(movsw_fast, 0)
+DEF(rep_movsw_fast, 0)
+DEF(stosw_fast, 0)
+DEF(rep_stosw_fast, 0)
+DEF(lodsw_fast, 0)
+DEF(rep_lodsw_fast, 0)
+DEF(scasw_fast, 0)
+DEF(repz_scasw_fast, 0)
+DEF(repnz_scasw_fast, 0)
+DEF(cmpsw_fast, 0)
+DEF(repz_cmpsw_fast, 0)
+DEF(repnz_cmpsw_fast, 0)
+DEF(outsw_fast, 0)
+DEF(rep_outsw_fast, 0)
+DEF(insw_fast, 0)
+DEF(rep_insw_fast, 0)
+DEF(movsw_a32, 0)
+DEF(rep_movsw_a32, 0)
+DEF(stosw_a32, 0)
+DEF(rep_stosw_a32, 0)
+DEF(lodsw_a32, 0)
+DEF(rep_lodsw_a32, 0)
+DEF(scasw_a32, 0)
+DEF(repz_scasw_a32, 0)
+DEF(repnz_scasw_a32, 0)
+DEF(cmpsw_a32, 0)
+DEF(repz_cmpsw_a32, 0)
+DEF(repnz_cmpsw_a32, 0)
+DEF(outsw_a32, 0)
+DEF(rep_outsw_a32, 0)
+DEF(insw_a32, 0)
+DEF(rep_insw_a32, 0)
+DEF(movsw_a16, 0)
+DEF(rep_movsw_a16, 0)
+DEF(stosw_a16, 0)
+DEF(rep_stosw_a16, 0)
+DEF(lodsw_a16, 0)
+DEF(rep_lodsw_a16, 0)
+DEF(scasw_a16, 0)
+DEF(repz_scasw_a16, 0)
+DEF(repnz_scasw_a16, 0)
+DEF(cmpsw_a16, 0)
+DEF(repz_cmpsw_a16, 0)
+DEF(repnz_cmpsw_a16, 0)
+DEF(outsw_a16, 0)
+DEF(rep_outsw_a16, 0)
+DEF(insw_a16, 0)
+DEF(rep_insw_a16, 0)
+DEF(outw_T0_T1, 0)
+DEF(inw_T0_T1, 0)
+DEF(jb_subl, 2)
+DEF(jz_subl, 2)
+DEF(jbe_subl, 2)
+DEF(js_subl, 2)
+DEF(jl_subl, 2)
+DEF(jle_subl, 2)
+DEF(loopnzl, 2)
+DEF(loopzl, 2)
+DEF(loopl, 2)
+DEF(jecxzl, 2)
+DEF(setb_T0_subl, 0)
+DEF(setz_T0_subl, 0)
+DEF(setbe_T0_subl, 0)
+DEF(sets_T0_subl, 0)
+DEF(setl_T0_subl, 0)
+DEF(setle_T0_subl, 0)
+DEF(roll_T0_T1_cc, 0)
+DEF(roll_T0_T1, 0)
+DEF(rorl_T0_T1_cc, 0)
+DEF(rorl_T0_T1, 0)
+DEF(rcll_T0_T1_cc, 0)
+DEF(rcrl_T0_T1_cc, 0)
+DEF(shll_T0_T1_cc, 0)
+DEF(shll_T0_T1, 0)
+DEF(shrl_T0_T1_cc, 0)
+DEF(shrl_T0_T1, 0)
+DEF(sarl_T0_T1_cc, 0)
+DEF(sarl_T0_T1, 0)
+DEF(shldl_T0_T1_im_cc, 1)
+DEF(shldl_T0_T1_ECX_cc, 0)
+DEF(shrdl_T0_T1_im_cc, 1)
+DEF(shrdl_T0_T1_ECX_cc, 0)
+DEF(adcl_T0_T1_cc, 0)
+DEF(sbbl_T0_T1_cc, 0)
+DEF(cmpxchgl_T0_T1_EAX_cc, 0)
+DEF(btl_T0_T1_cc, 0)
+DEF(btsl_T0_T1_cc, 0)
+DEF(btrl_T0_T1_cc, 0)
+DEF(btcl_T0_T1_cc, 0)
+DEF(bsfl_T0_cc, 0)
+DEF(bsrl_T0_cc, 0)
+DEF(movsl_fast, 0)
+DEF(rep_movsl_fast, 0)
+DEF(stosl_fast, 0)
+DEF(rep_stosl_fast, 0)
+DEF(lodsl_fast, 0)
+DEF(rep_lodsl_fast, 0)
+DEF(scasl_fast, 0)
+DEF(repz_scasl_fast, 0)
+DEF(repnz_scasl_fast, 0)
+DEF(cmpsl_fast, 0)
+DEF(repz_cmpsl_fast, 0)
+DEF(repnz_cmpsl_fast, 0)
+DEF(outsl_fast, 0)
+DEF(rep_outsl_fast, 0)
+DEF(insl_fast, 0)
+DEF(rep_insl_fast, 0)
+DEF(movsl_a32, 0)
+DEF(rep_movsl_a32, 0)
+DEF(stosl_a32, 0)
+DEF(rep_stosl_a32, 0)
+DEF(lodsl_a32, 0)
+DEF(rep_lodsl_a32, 0)
+DEF(scasl_a32, 0)
+DEF(repz_scasl_a32, 0)
+DEF(repnz_scasl_a32, 0)
+DEF(cmpsl_a32, 0)
+DEF(repz_cmpsl_a32, 0)
+DEF(repnz_cmpsl_a32, 0)
+DEF(outsl_a32, 0)
+DEF(rep_outsl_a32, 0)
+DEF(insl_a32, 0)
+DEF(rep_insl_a32, 0)
+DEF(movsl_a16, 0)
+DEF(rep_movsl_a16, 0)
+DEF(stosl_a16, 0)
+DEF(rep_stosl_a16, 0)
+DEF(lodsl_a16, 0)
+DEF(rep_lodsl_a16, 0)
+DEF(scasl_a16, 0)
+DEF(repz_scasl_a16, 0)
+DEF(repnz_scasl_a16, 0)
+DEF(cmpsl_a16, 0)
+DEF(repz_cmpsl_a16, 0)
+DEF(repnz_cmpsl_a16, 0)
+DEF(outsl_a16, 0)
+DEF(rep_outsl_a16, 0)
+DEF(insl_a16, 0)
+DEF(rep_insl_a16, 0)
+DEF(outl_T0_T1, 0)
+DEF(inl_T0_T1, 0)
+DEF(movsbl_T0_T0, 0)
+DEF(movzbl_T0_T0, 0)
+DEF(movswl_T0_T0, 0)
+DEF(movzwl_T0_T0, 0)
+DEF(movswl_EAX_AX, 0)
+DEF(movsbw_AX_AL, 0)
+DEF(movslq_EDX_EAX, 0)
+DEF(movswl_DX_AX, 0)
+DEF(pushl_T0, 0)
+DEF(pushw_T0, 0)
+DEF(pushl_ss32_T0, 0)
+DEF(pushw_ss32_T0, 0)
+DEF(pushl_ss16_T0, 0)
+DEF(pushw_ss16_T0, 0)
+DEF(popl_T0, 0)
+DEF(popw_T0, 0)
+DEF(popl_ss32_T0, 0)
+DEF(popw_ss32_T0, 0)
+DEF(popl_ss16_T0, 0)
+DEF(popw_ss16_T0, 0)
+DEF(addl_ESP_4, 0)
+DEF(addl_ESP_2, 0)
+DEF(addw_ESP_4, 0)
+DEF(addw_ESP_2, 0)
+DEF(addl_ESP_im, 1)
+DEF(addw_ESP_im, 1)
+DEF(rdtsc, 0)
+DEF(cpuid, 0)
+DEF(aam, 1)
+DEF(aad, 1)
+DEF(aaa, 0)
+DEF(aas, 0)
+DEF(daa, 0)
+DEF(das, 0)
+DEF(movl_seg_T0, 1)
+DEF(movl_T0_seg, 1)
+DEF(movl_A0_seg, 1)
+DEF(addl_A0_seg, 1)
+DEF(jo_cc, 2)
+DEF(jb_cc, 2)
+DEF(jz_cc, 2)
+DEF(jbe_cc, 2)
+DEF(js_cc, 2)
+DEF(jp_cc, 2)
+DEF(jl_cc, 2)
+DEF(jle_cc, 2)
+DEF(seto_T0_cc, 0)
+DEF(setb_T0_cc, 0)
+DEF(setz_T0_cc, 0)
+DEF(setbe_T0_cc, 0)
+DEF(sets_T0_cc, 0)
+DEF(setp_T0_cc, 0)
+DEF(setl_T0_cc, 0)
+DEF(setle_T0_cc, 0)
+DEF(xor_T0_1, 0)
+DEF(set_cc_op, 1)
+DEF(movl_eflags_T0, 0)
+DEF(movb_eflags_T0, 0)
+DEF(movl_T0_eflags, 0)
+DEF(cld, 0)
+DEF(std, 0)
+DEF(clc, 0)
+DEF(stc, 0)
+DEF(cmc, 0)
+DEF(salc, 0)
+DEF(flds_FT0_A0, 0)
+DEF(fldl_FT0_A0, 0)
+DEF(fild_FT0_A0, 0)
+DEF(fildl_FT0_A0, 0)
+DEF(fildll_FT0_A0, 0)
+DEF(flds_ST0_A0, 0)
+DEF(fldl_ST0_A0, 0)
+DEF(fldt_ST0_A0, 0)
+DEF(fild_ST0_A0, 0)
+DEF(fildl_ST0_A0, 0)
+DEF(fildll_ST0_A0, 0)
+DEF(fsts_ST0_A0, 0)
+DEF(fstl_ST0_A0, 0)
+DEF(fstt_ST0_A0, 0)
+DEF(fist_ST0_A0, 0)
+DEF(fistl_ST0_A0, 0)
+DEF(fistll_ST0_A0, 0)
+DEF(fbld_ST0_A0, 0)
+DEF(fbst_ST0_A0, 0)
+DEF(fpush, 0)
+DEF(fpop, 0)
+DEF(fdecstp, 0)
+DEF(fincstp, 0)
+DEF(fmov_ST0_FT0, 0)
+DEF(fmov_FT0_STN, 1)
+DEF(fmov_ST0_STN, 1)
+DEF(fmov_STN_ST0, 1)
+DEF(fxchg_ST0_STN, 1)
+DEF(fcom_ST0_FT0, 0)
+DEF(fucom_ST0_FT0, 0)
+DEF(fadd_ST0_FT0, 0)
+DEF(fmul_ST0_FT0, 0)
+DEF(fsub_ST0_FT0, 0)
+DEF(fsubr_ST0_FT0, 0)
+DEF(fdiv_ST0_FT0, 0)
+DEF(fdivr_ST0_FT0, 0)
+DEF(fadd_STN_ST0, 1)
+DEF(fmul_STN_ST0, 1)
+DEF(fsub_STN_ST0, 1)
+DEF(fsubr_STN_ST0, 1)
+DEF(fdiv_STN_ST0, 1)
+DEF(fdivr_STN_ST0, 1)
+DEF(fchs_ST0, 0)
+DEF(fabs_ST0, 0)
+DEF(fxam_ST0, 0)
+DEF(fld1_ST0, 0)
+DEF(fldl2t_ST0, 0)
+DEF(fldl2e_ST0, 0)
+DEF(fldpi_ST0, 0)
+DEF(fldlg2_ST0, 0)
+DEF(fldln2_ST0, 0)
+DEF(fldz_ST0, 0)
+DEF(fldz_FT0, 0)
+DEF(f2xm1, 0)
+DEF(fyl2x, 0)
+DEF(fptan, 0)
+DEF(fpatan, 0)
+DEF(fxtract, 0)
+DEF(fprem1, 0)
+DEF(fprem, 0)
+DEF(fyl2xp1, 0)
+DEF(fsqrt, 0)
+DEF(fsincos, 0)
+DEF(frndint, 0)
+DEF(fscale, 0)
+DEF(fsin, 0)
+DEF(fcos, 0)
+DEF(fnstsw_A0, 0)
+DEF(fnstsw_EAX, 0)
+DEF(fnstcw_A0, 0)
+DEF(fldcw_A0, 0)
+DEF(fclex, 0)
+DEF(fninit, 0)
+DEF(lock, 0)
+DEF(unlock, 0)