target/arm: Convert BRA[AB]Z, BLR[AB]Z, RETA[AB] to decodetree
Convert the single-register pointer-authentication variants of BR, BLR, RET to decodetree. (BRAA/BLRAA are in a different branch of the legacy decoder and will be dealt with in the next commit.) Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20230512144106.3608981-19-peter.maydell@linaro.org
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@ -131,3 +131,10 @@ B_cond 0101010 0 ................... 0 cond:4 imm=%imm19
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BR 1101011 0000 11111 000000 rn:5 00000 &r
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BLR 1101011 0001 11111 000000 rn:5 00000 &r
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RET 1101011 0010 11111 000000 rn:5 00000 &r
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&braz rn m
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BRAZ 1101011 0000 11111 00001 m:1 rn:5 11111 &braz # BRAAZ, BRABZ
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BLRAZ 1101011 0001 11111 00001 m:1 rn:5 11111 &braz # BLRAAZ, BLRABZ
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&reta m
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RETA 1101011 0010 11111 00001 m:1 11111 11111 &reta # RETAA, RETAB
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@ -1435,6 +1435,75 @@ static bool trans_RET(DisasContext *s, arg_r *a)
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return true;
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}
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static TCGv_i64 auth_branch_target(DisasContext *s, TCGv_i64 dst,
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TCGv_i64 modifier, bool use_key_a)
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{
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TCGv_i64 truedst;
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/*
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* Return the branch target for a BRAA/RETA/etc, which is either
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* just the destination dst, or that value with the pauth check
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* done and the code removed from the high bits.
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*/
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if (!s->pauth_active) {
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return dst;
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}
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truedst = tcg_temp_new_i64();
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if (use_key_a) {
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gen_helper_autia(truedst, cpu_env, dst, modifier);
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} else {
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gen_helper_autib(truedst, cpu_env, dst, modifier);
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}
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return truedst;
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}
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static bool trans_BRAZ(DisasContext *s, arg_braz *a)
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{
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TCGv_i64 dst;
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if (!dc_isar_feature(aa64_pauth, s)) {
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return false;
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}
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dst = auth_branch_target(s, cpu_reg(s, a->rn), tcg_constant_i64(0), !a->m);
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gen_a64_set_pc(s, dst);
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set_btype_for_br(s, a->rn);
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s->base.is_jmp = DISAS_JUMP;
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return true;
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}
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static bool trans_BLRAZ(DisasContext *s, arg_braz *a)
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{
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TCGv_i64 dst, lr;
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if (!dc_isar_feature(aa64_pauth, s)) {
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return false;
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}
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dst = auth_branch_target(s, cpu_reg(s, a->rn), tcg_constant_i64(0), !a->m);
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lr = cpu_reg(s, 30);
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if (dst == lr) {
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TCGv_i64 tmp = tcg_temp_new_i64();
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tcg_gen_mov_i64(tmp, dst);
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dst = tmp;
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}
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gen_pc_plus_diff(s, lr, curr_insn_len(s));
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gen_a64_set_pc(s, dst);
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set_btype_for_blr(s);
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s->base.is_jmp = DISAS_JUMP;
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return true;
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}
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static bool trans_RETA(DisasContext *s, arg_reta *a)
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{
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TCGv_i64 dst;
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dst = auth_branch_target(s, cpu_reg(s, 30), cpu_X[31], !a->m);
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gen_a64_set_pc(s, dst);
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s->base.is_jmp = DISAS_JUMP;
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return true;
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}
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/* HINT instruction group, including various allocated HINTs */
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static void handle_hint(DisasContext *s, uint32_t insn,
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unsigned int op1, unsigned int op2, unsigned int crm)
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@ -2227,61 +2296,14 @@ static void disas_uncond_b_reg(DisasContext *s, uint32_t insn)
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}
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switch (opc) {
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case 0: /* BR */
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case 1: /* BLR */
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case 2: /* RET */
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btype_mod = opc;
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switch (op3) {
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case 0:
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/* BR, BLR, RET : handled in decodetree */
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goto do_unallocated;
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case 2:
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case 3:
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if (!dc_isar_feature(aa64_pauth, s)) {
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goto do_unallocated;
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}
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if (opc == 2) {
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/* RETAA, RETAB */
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if (rn != 0x1f || op4 != 0x1f) {
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goto do_unallocated;
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}
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rn = 30;
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modifier = cpu_X[31];
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} else {
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/* BRAAZ, BRABZ, BLRAAZ, BLRABZ */
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if (op4 != 0x1f) {
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goto do_unallocated;
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}
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modifier = tcg_constant_i64(0);
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}
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if (s->pauth_active) {
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dst = tcg_temp_new_i64();
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if (op3 == 2) {
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gen_helper_autia(dst, cpu_env, cpu_reg(s, rn), modifier);
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} else {
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gen_helper_autib(dst, cpu_env, cpu_reg(s, rn), modifier);
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}
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} else {
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dst = cpu_reg(s, rn);
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}
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break;
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default:
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goto do_unallocated;
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}
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/* BLR also needs to load return address */
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if (opc == 1) {
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TCGv_i64 lr = cpu_reg(s, 30);
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if (dst == lr) {
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TCGv_i64 tmp = tcg_temp_new_i64();
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tcg_gen_mov_i64(tmp, dst);
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dst = tmp;
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}
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gen_pc_plus_diff(s, lr, curr_insn_len(s));
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}
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gen_a64_set_pc(s, dst);
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break;
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case 0:
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case 1:
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case 2:
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/*
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* BR, BLR, RET, RETAA, RETAB, BRAAZ, BRABZ, BLRAAZ, BLRABZ:
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* handled in decodetree
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*/
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goto do_unallocated;
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case 8: /* BRAA */
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case 9: /* BLRAA */
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