hw/nvme updates
performance improvements by Jinhao ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ * shadow doorbells * ioeventfd plus some misc fixes (Darren, Niklas). -----BEGIN PGP SIGNATURE----- iQEzBAABCAAdFiEEUigzqnXi3OaiR2bATeGvMW1PDekFAmLRKGwACgkQTeGvMW1P Deki7Af9Hg0ltW9RyxzUtYB5hwaMpgrHHcViBoLK8mt7wa5hh5luFb1P3/+yltUG LU/cws93mq3jDy30dKnVa5+xugDmuEy470OxjJPCivLEpV6qpONulp+iHFIKim4N kPXX8K1R4XVTVvCFFpmub6GUCFZpXRVW9uPAAL96BzaSjEK7K+5H3boJ7HfT5YUY Tx9LuPQUcIUHViF/4wNU0Sqx15PoOOjHqSnA3EjCDCscqPkbhaoEoyI5Pk+BMxzf tElNh/ffP5x0BSaKOofdtW+iHaxlSgPJ6IA0W9dwXJyRCvoaa9near2iGXDa6PEA bRpQpudzIkL3Swfgcm4D+N7NQbCSOg== =Wg5B -----END PGP SIGNATURE----- Merge tag 'nvme-next-pull-request' of git://git.infradead.org/qemu-nvme into staging hw/nvme updates performance improvements by Jinhao ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ * shadow doorbells * ioeventfd plus some misc fixes (Darren, Niklas). # gpg: Signature made Fri 15 Jul 2022 09:42:20 BST # gpg: using RSA key 522833AA75E2DCE6A24766C04DE1AF316D4F0DE9 # gpg: Good signature from "Klaus Jensen <its@irrelevant.dk>" [unknown] # gpg: aka "Klaus Jensen <k.jensen@samsung.com>" [unknown] # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: DDCA 4D9C 9EF9 31CC 3468 4272 63D5 6FC5 E55D A838 # Subkey fingerprint: 5228 33AA 75E2 DCE6 A247 66C0 4DE1 AF31 6D4F 0DE9 * tag 'nvme-next-pull-request' of git://git.infradead.org/qemu-nvme: hw/nvme: Use ioeventfd to handle doorbell updates nvme: Fix misleading macro when mixed with ternary operator hw/nvme: force nvme-ns param 'shared' to false if no nvme-subsys node hw/nvme: fix example serial in documentation hw/nvme: Add trace events for shadow doorbell buffer hw/nvme: Implement shadow doorbell buffer support Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Peter Maydell
commit
0ebf76aae5
@ -104,8 +104,8 @@ multipath I/O.
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.. code-block:: console
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-device nvme-subsys,id=nvme-subsys-0,nqn=subsys0
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-device nvme,serial=a,subsys=nvme-subsys-0
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-device nvme,serial=b,subsys=nvme-subsys-0
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-device nvme,serial=deadbeef,subsys=nvme-subsys-0
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-device nvme,serial=deadbeef,subsys=nvme-subsys-0
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This will create an NVM subsystem with two controllers. Having controllers
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linked to an ``nvme-subsys`` device allows additional ``nvme-ns`` parameters:
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233
hw/nvme/ctrl.c
233
hw/nvme/ctrl.c
@ -264,6 +264,7 @@ static const uint32_t nvme_cse_acs[256] = {
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[NVME_ADM_CMD_ASYNC_EV_REQ] = NVME_CMD_EFF_CSUPP,
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[NVME_ADM_CMD_NS_ATTACHMENT] = NVME_CMD_EFF_CSUPP | NVME_CMD_EFF_NIC,
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[NVME_ADM_CMD_VIRT_MNGMT] = NVME_CMD_EFF_CSUPP,
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[NVME_ADM_CMD_DBBUF_CONFIG] = NVME_CMD_EFF_CSUPP,
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[NVME_ADM_CMD_FORMAT_NVM] = NVME_CMD_EFF_CSUPP | NVME_CMD_EFF_LBCC,
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};
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@ -1330,6 +1331,13 @@ static inline void nvme_blk_write(BlockBackend *blk, int64_t offset,
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}
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}
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static void nvme_update_cq_head(NvmeCQueue *cq)
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{
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pci_dma_read(&cq->ctrl->parent_obj, cq->db_addr, &cq->head,
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sizeof(cq->head));
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trace_pci_nvme_shadow_doorbell_cq(cq->cqid, cq->head);
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}
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static void nvme_post_cqes(void *opaque)
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{
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NvmeCQueue *cq = opaque;
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@ -1342,6 +1350,10 @@ static void nvme_post_cqes(void *opaque)
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NvmeSQueue *sq;
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hwaddr addr;
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if (n->dbbuf_enabled) {
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nvme_update_cq_head(cq);
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}
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if (nvme_cq_full(cq)) {
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break;
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}
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@ -1388,7 +1400,14 @@ static void nvme_enqueue_req_completion(NvmeCQueue *cq, NvmeRequest *req)
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QTAILQ_REMOVE(&req->sq->out_req_list, req, entry);
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QTAILQ_INSERT_TAIL(&cq->req_list, req, entry);
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timer_mod(cq->timer, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + 500);
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if (req->sq->ioeventfd_enabled) {
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/* Post CQE directly since we are in main loop thread */
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nvme_post_cqes(cq);
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} else {
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/* Schedule the timer to post CQE later since we are in vcpu thread */
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timer_mod(cq->timer, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + 500);
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}
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}
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static void nvme_process_aers(void *opaque)
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@ -4214,10 +4233,82 @@ static uint16_t nvme_io_cmd(NvmeCtrl *n, NvmeRequest *req)
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return NVME_INVALID_OPCODE | NVME_DNR;
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}
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static void nvme_cq_notifier(EventNotifier *e)
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{
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NvmeCQueue *cq = container_of(e, NvmeCQueue, notifier);
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NvmeCtrl *n = cq->ctrl;
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event_notifier_test_and_clear(&cq->notifier);
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nvme_update_cq_head(cq);
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if (cq->tail == cq->head) {
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if (cq->irq_enabled) {
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n->cq_pending--;
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}
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nvme_irq_deassert(n, cq);
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}
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nvme_post_cqes(cq);
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}
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static int nvme_init_cq_ioeventfd(NvmeCQueue *cq)
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{
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NvmeCtrl *n = cq->ctrl;
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uint16_t offset = (cq->cqid << 3) + (1 << 2);
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int ret;
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ret = event_notifier_init(&cq->notifier, 0);
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if (ret < 0) {
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return ret;
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}
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event_notifier_set_handler(&cq->notifier, nvme_cq_notifier);
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memory_region_add_eventfd(&n->iomem,
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0x1000 + offset, 4, false, 0, &cq->notifier);
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return 0;
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}
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static void nvme_sq_notifier(EventNotifier *e)
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{
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NvmeSQueue *sq = container_of(e, NvmeSQueue, notifier);
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event_notifier_test_and_clear(&sq->notifier);
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nvme_process_sq(sq);
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}
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static int nvme_init_sq_ioeventfd(NvmeSQueue *sq)
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{
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NvmeCtrl *n = sq->ctrl;
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uint16_t offset = sq->sqid << 3;
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int ret;
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ret = event_notifier_init(&sq->notifier, 0);
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if (ret < 0) {
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return ret;
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}
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event_notifier_set_handler(&sq->notifier, nvme_sq_notifier);
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memory_region_add_eventfd(&n->iomem,
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0x1000 + offset, 4, false, 0, &sq->notifier);
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return 0;
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}
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static void nvme_free_sq(NvmeSQueue *sq, NvmeCtrl *n)
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{
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uint16_t offset = sq->sqid << 3;
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n->sq[sq->sqid] = NULL;
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timer_free(sq->timer);
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if (sq->ioeventfd_enabled) {
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memory_region_del_eventfd(&n->iomem,
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0x1000 + offset, 4, false, 0, &sq->notifier);
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event_notifier_cleanup(&sq->notifier);
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}
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g_free(sq->io_req);
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if (sq->sqid) {
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g_free(sq);
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@ -4287,6 +4378,17 @@ static void nvme_init_sq(NvmeSQueue *sq, NvmeCtrl *n, uint64_t dma_addr,
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}
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sq->timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, nvme_process_sq, sq);
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if (n->dbbuf_enabled) {
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sq->db_addr = n->dbbuf_dbs + (sqid << 3);
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sq->ei_addr = n->dbbuf_eis + (sqid << 3);
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if (n->params.ioeventfd && sq->sqid != 0) {
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if (!nvme_init_sq_ioeventfd(sq)) {
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sq->ioeventfd_enabled = true;
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}
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}
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}
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assert(n->cq[cqid]);
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cq = n->cq[cqid];
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QTAILQ_INSERT_TAIL(&(cq->sq_list), sq, entry);
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@ -4588,8 +4690,15 @@ static uint16_t nvme_get_log(NvmeCtrl *n, NvmeRequest *req)
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static void nvme_free_cq(NvmeCQueue *cq, NvmeCtrl *n)
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{
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uint16_t offset = (cq->cqid << 3) + (1 << 2);
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n->cq[cq->cqid] = NULL;
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timer_free(cq->timer);
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if (cq->ioeventfd_enabled) {
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memory_region_del_eventfd(&n->iomem,
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0x1000 + offset, 4, false, 0, &cq->notifier);
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event_notifier_cleanup(&cq->notifier);
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}
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if (msix_enabled(&n->parent_obj)) {
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msix_vector_unuse(&n->parent_obj, cq->vector);
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}
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@ -4645,6 +4754,16 @@ static void nvme_init_cq(NvmeCQueue *cq, NvmeCtrl *n, uint64_t dma_addr,
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cq->head = cq->tail = 0;
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QTAILQ_INIT(&cq->req_list);
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QTAILQ_INIT(&cq->sq_list);
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if (n->dbbuf_enabled) {
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cq->db_addr = n->dbbuf_dbs + (cqid << 3) + (1 << 2);
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cq->ei_addr = n->dbbuf_eis + (cqid << 3) + (1 << 2);
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if (n->params.ioeventfd && cqid != 0) {
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if (!nvme_init_cq_ioeventfd(cq)) {
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cq->ioeventfd_enabled = true;
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}
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}
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}
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n->cq[cqid] = cq;
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cq->timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, nvme_post_cqes, cq);
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}
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@ -5988,6 +6107,64 @@ static uint16_t nvme_virt_mngmt(NvmeCtrl *n, NvmeRequest *req)
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}
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}
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static uint16_t nvme_dbbuf_config(NvmeCtrl *n, const NvmeRequest *req)
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{
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uint64_t dbs_addr = le64_to_cpu(req->cmd.dptr.prp1);
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uint64_t eis_addr = le64_to_cpu(req->cmd.dptr.prp2);
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int i;
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/* Address should be page aligned */
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if (dbs_addr & (n->page_size - 1) || eis_addr & (n->page_size - 1)) {
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return NVME_INVALID_FIELD | NVME_DNR;
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}
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/* Save shadow buffer base addr for use during queue creation */
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n->dbbuf_dbs = dbs_addr;
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n->dbbuf_eis = eis_addr;
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n->dbbuf_enabled = true;
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for (i = 0; i < n->params.max_ioqpairs + 1; i++) {
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NvmeSQueue *sq = n->sq[i];
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NvmeCQueue *cq = n->cq[i];
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if (sq) {
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/*
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* CAP.DSTRD is 0, so offset of ith sq db_addr is (i<<3)
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* nvme_process_db() uses this hard-coded way to calculate
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* doorbell offsets. Be consistent with that here.
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*/
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sq->db_addr = dbs_addr + (i << 3);
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sq->ei_addr = eis_addr + (i << 3);
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pci_dma_write(&n->parent_obj, sq->db_addr, &sq->tail,
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sizeof(sq->tail));
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if (n->params.ioeventfd && sq->sqid != 0) {
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if (!nvme_init_sq_ioeventfd(sq)) {
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sq->ioeventfd_enabled = true;
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}
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}
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}
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if (cq) {
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/* CAP.DSTRD is 0, so offset of ith cq db_addr is (i<<3)+(1<<2) */
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cq->db_addr = dbs_addr + (i << 3) + (1 << 2);
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cq->ei_addr = eis_addr + (i << 3) + (1 << 2);
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pci_dma_write(&n->parent_obj, cq->db_addr, &cq->head,
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sizeof(cq->head));
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if (n->params.ioeventfd && cq->cqid != 0) {
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if (!nvme_init_cq_ioeventfd(cq)) {
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cq->ioeventfd_enabled = true;
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}
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}
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}
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}
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trace_pci_nvme_dbbuf_config(dbs_addr, eis_addr);
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return NVME_SUCCESS;
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}
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static uint16_t nvme_admin_cmd(NvmeCtrl *n, NvmeRequest *req)
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{
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trace_pci_nvme_admin_cmd(nvme_cid(req), nvme_sqid(req), req->cmd.opcode,
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@ -6032,6 +6209,8 @@ static uint16_t nvme_admin_cmd(NvmeCtrl *n, NvmeRequest *req)
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return nvme_ns_attachment(n, req);
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case NVME_ADM_CMD_VIRT_MNGMT:
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return nvme_virt_mngmt(n, req);
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case NVME_ADM_CMD_DBBUF_CONFIG:
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return nvme_dbbuf_config(n, req);
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case NVME_ADM_CMD_FORMAT_NVM:
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return nvme_format(n, req);
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default:
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@ -6041,6 +6220,20 @@ static uint16_t nvme_admin_cmd(NvmeCtrl *n, NvmeRequest *req)
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return NVME_INVALID_OPCODE | NVME_DNR;
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}
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static void nvme_update_sq_eventidx(const NvmeSQueue *sq)
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{
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pci_dma_write(&sq->ctrl->parent_obj, sq->ei_addr, &sq->tail,
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sizeof(sq->tail));
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trace_pci_nvme_eventidx_sq(sq->sqid, sq->tail);
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}
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static void nvme_update_sq_tail(NvmeSQueue *sq)
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{
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pci_dma_read(&sq->ctrl->parent_obj, sq->db_addr, &sq->tail,
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sizeof(sq->tail));
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trace_pci_nvme_shadow_doorbell_sq(sq->sqid, sq->tail);
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}
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static void nvme_process_sq(void *opaque)
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{
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NvmeSQueue *sq = opaque;
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@ -6052,6 +6245,10 @@ static void nvme_process_sq(void *opaque)
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NvmeCmd cmd;
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NvmeRequest *req;
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if (n->dbbuf_enabled) {
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nvme_update_sq_tail(sq);
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}
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while (!(nvme_sq_empty(sq) || QTAILQ_EMPTY(&sq->req_list))) {
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addr = sq->dma_addr + sq->head * n->sqe_size;
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if (nvme_addr_read(n, addr, (void *)&cmd, sizeof(cmd))) {
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@ -6075,6 +6272,11 @@ static void nvme_process_sq(void *opaque)
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req->status = status;
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nvme_enqueue_req_completion(cq, req);
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}
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if (n->dbbuf_enabled) {
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nvme_update_sq_eventidx(sq);
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nvme_update_sq_tail(sq);
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}
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}
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}
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@ -6184,6 +6386,10 @@ static void nvme_ctrl_reset(NvmeCtrl *n, NvmeResetType rst)
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stl_le_p(&n->bar.intms, 0);
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stl_le_p(&n->bar.intmc, 0);
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stl_le_p(&n->bar.cc, 0);
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n->dbbuf_dbs = 0;
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n->dbbuf_eis = 0;
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n->dbbuf_enabled = false;
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}
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static void nvme_ctrl_shutdown(NvmeCtrl *n)
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@ -6694,6 +6900,10 @@ static void nvme_process_db(NvmeCtrl *n, hwaddr addr, int val)
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start_sqs = nvme_cq_full(cq) ? 1 : 0;
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cq->head = new_head;
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if (!qid && n->dbbuf_enabled) {
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pci_dma_write(&n->parent_obj, cq->db_addr, &cq->head,
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sizeof(cq->head));
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}
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if (start_sqs) {
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NvmeSQueue *sq;
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QTAILQ_FOREACH(sq, &cq->sq_list, entry) {
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@ -6751,6 +6961,23 @@ static void nvme_process_db(NvmeCtrl *n, hwaddr addr, int val)
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trace_pci_nvme_mmio_doorbell_sq(sq->sqid, new_tail);
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sq->tail = new_tail;
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if (!qid && n->dbbuf_enabled) {
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/*
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* The spec states "the host shall also update the controller's
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* corresponding doorbell property to match the value of that entry
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* in the Shadow Doorbell buffer."
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*
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* Since this context is currently a VM trap, we can safely enforce
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* the requirement from the device side in case the host is
|
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* misbehaving.
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*
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* Note, we shouldn't have to do this, but various drivers
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* including ones that run on Linux, are not updating Admin Queues,
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* so we can't trust reading it for an appropriate sq tail.
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*/
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pci_dma_write(&n->parent_obj, sq->db_addr, &sq->tail,
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sizeof(sq->tail));
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}
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timer_mod(sq->timer, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + 500);
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}
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}
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@ -7231,7 +7458,8 @@ static void nvme_init_ctrl(NvmeCtrl *n, PCIDevice *pci_dev)
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id->mdts = n->params.mdts;
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id->ver = cpu_to_le32(NVME_SPEC_VER);
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id->oacs = cpu_to_le16(NVME_OACS_NS_MGMT | NVME_OACS_FORMAT);
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id->oacs =
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cpu_to_le16(NVME_OACS_NS_MGMT | NVME_OACS_FORMAT | NVME_OACS_DBBUF);
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id->cntrltype = 0x1;
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/*
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@ -7436,6 +7664,7 @@ static Property nvme_props[] = {
|
||||
DEFINE_PROP_UINT8("vsl", NvmeCtrl, params.vsl, 7),
|
||||
DEFINE_PROP_BOOL("use-intel-id", NvmeCtrl, params.use_intel_id, false),
|
||||
DEFINE_PROP_BOOL("legacy-cmb", NvmeCtrl, params.legacy_cmb, false),
|
||||
DEFINE_PROP_BOOL("ioeventfd", NvmeCtrl, params.ioeventfd, true),
|
||||
DEFINE_PROP_UINT8("zoned.zasl", NvmeCtrl, params.zasl, 0),
|
||||
DEFINE_PROP_BOOL("zoned.auto_transition", NvmeCtrl,
|
||||
params.auto_transition_zones, true),
|
||||
|
||||
@ -546,6 +546,8 @@ static void nvme_ns_realize(DeviceState *dev, Error **errp)
|
||||
int i;
|
||||
|
||||
if (!n->subsys) {
|
||||
/* If no subsys, the ns cannot be attached to more than one ctrl. */
|
||||
ns->params.shared = false;
|
||||
if (ns->params.detached) {
|
||||
error_setg(errp, "detached requires that the nvme device is "
|
||||
"linked to an nvme-subsys device");
|
||||
|
||||
@ -341,6 +341,7 @@ static inline const char *nvme_adm_opc_str(uint8_t opc)
|
||||
case NVME_ADM_CMD_ASYNC_EV_REQ: return "NVME_ADM_CMD_ASYNC_EV_REQ";
|
||||
case NVME_ADM_CMD_NS_ATTACHMENT: return "NVME_ADM_CMD_NS_ATTACHMENT";
|
||||
case NVME_ADM_CMD_VIRT_MNGMT: return "NVME_ADM_CMD_VIRT_MNGMT";
|
||||
case NVME_ADM_CMD_DBBUF_CONFIG: return "NVME_ADM_CMD_DBBUF_CONFIG";
|
||||
case NVME_ADM_CMD_FORMAT_NVM: return "NVME_ADM_CMD_FORMAT_NVM";
|
||||
default: return "NVME_ADM_CMD_UNKNOWN";
|
||||
}
|
||||
@ -372,7 +373,11 @@ typedef struct NvmeSQueue {
|
||||
uint32_t tail;
|
||||
uint32_t size;
|
||||
uint64_t dma_addr;
|
||||
uint64_t db_addr;
|
||||
uint64_t ei_addr;
|
||||
QEMUTimer *timer;
|
||||
EventNotifier notifier;
|
||||
bool ioeventfd_enabled;
|
||||
NvmeRequest *io_req;
|
||||
QTAILQ_HEAD(, NvmeRequest) req_list;
|
||||
QTAILQ_HEAD(, NvmeRequest) out_req_list;
|
||||
@ -389,7 +394,11 @@ typedef struct NvmeCQueue {
|
||||
uint32_t vector;
|
||||
uint32_t size;
|
||||
uint64_t dma_addr;
|
||||
uint64_t db_addr;
|
||||
uint64_t ei_addr;
|
||||
QEMUTimer *timer;
|
||||
EventNotifier notifier;
|
||||
bool ioeventfd_enabled;
|
||||
QTAILQ_HEAD(, NvmeSQueue) sq_list;
|
||||
QTAILQ_HEAD(, NvmeRequest) req_list;
|
||||
} NvmeCQueue;
|
||||
@ -412,6 +421,7 @@ typedef struct NvmeParams {
|
||||
uint8_t zasl;
|
||||
bool auto_transition_zones;
|
||||
bool legacy_cmb;
|
||||
bool ioeventfd;
|
||||
uint8_t sriov_max_vfs;
|
||||
uint16_t sriov_vq_flexible;
|
||||
uint16_t sriov_vi_flexible;
|
||||
@ -445,6 +455,9 @@ typedef struct NvmeCtrl {
|
||||
uint8_t smart_critical_warning;
|
||||
uint32_t conf_msix_qsize;
|
||||
uint32_t conf_ioqpairs;
|
||||
uint64_t dbbuf_dbs;
|
||||
uint64_t dbbuf_eis;
|
||||
bool dbbuf_enabled;
|
||||
|
||||
struct {
|
||||
MemoryRegion mem;
|
||||
|
||||
@ -3,6 +3,7 @@ pci_nvme_irq_msix(uint32_t vector) "raising MSI-X IRQ vector %u"
|
||||
pci_nvme_irq_pin(void) "pulsing IRQ pin"
|
||||
pci_nvme_irq_masked(void) "IRQ is masked"
|
||||
pci_nvme_dma_read(uint64_t prp1, uint64_t prp2) "DMA read, prp1=0x%"PRIx64" prp2=0x%"PRIx64""
|
||||
pci_nvme_dbbuf_config(uint64_t dbs_addr, uint64_t eis_addr) "dbs_addr=0x%"PRIx64" eis_addr=0x%"PRIx64""
|
||||
pci_nvme_map_addr(uint64_t addr, uint64_t len) "addr 0x%"PRIx64" len %"PRIu64""
|
||||
pci_nvme_map_addr_cmb(uint64_t addr, uint64_t len) "addr 0x%"PRIx64" len %"PRIu64""
|
||||
pci_nvme_map_prp(uint64_t trans_len, uint32_t len, uint64_t prp1, uint64_t prp2, int num_prps) "trans_len %"PRIu64" len %"PRIu32" prp1 0x%"PRIx64" prp2 0x%"PRIx64" num_prps %d"
|
||||
@ -83,6 +84,8 @@ pci_nvme_enqueue_event_noqueue(int queued) "queued %d"
|
||||
pci_nvme_enqueue_event_masked(uint8_t typ) "type 0x%"PRIx8""
|
||||
pci_nvme_no_outstanding_aers(void) "ignoring event; no outstanding AERs"
|
||||
pci_nvme_enqueue_req_completion(uint16_t cid, uint16_t cqid, uint32_t dw0, uint32_t dw1, uint16_t status) "cid %"PRIu16" cqid %"PRIu16" dw0 0x%"PRIx32" dw1 0x%"PRIx32" status 0x%"PRIx16""
|
||||
pci_nvme_eventidx_cq(uint16_t cqid, uint16_t new_eventidx) "cqid %"PRIu16" new_eventidx %"PRIu16""
|
||||
pci_nvme_eventidx_sq(uint16_t sqid, uint16_t new_eventidx) "sqid %"PRIu16" new_eventidx %"PRIu16""
|
||||
pci_nvme_mmio_read(uint64_t addr, unsigned size) "addr 0x%"PRIx64" size %d"
|
||||
pci_nvme_mmio_write(uint64_t addr, uint64_t data, unsigned size) "addr 0x%"PRIx64" data 0x%"PRIx64" size %d"
|
||||
pci_nvme_mmio_doorbell_cq(uint16_t cqid, uint16_t new_head) "cqid %"PRIu16" new_head %"PRIu16""
|
||||
@ -99,6 +102,8 @@ pci_nvme_mmio_start_success(void) "setting controller enable bit succeeded"
|
||||
pci_nvme_mmio_stopped(void) "cleared controller enable bit"
|
||||
pci_nvme_mmio_shutdown_set(void) "shutdown bit set"
|
||||
pci_nvme_mmio_shutdown_cleared(void) "shutdown bit cleared"
|
||||
pci_nvme_shadow_doorbell_cq(uint16_t cqid, uint16_t new_shadow_doorbell) "cqid %"PRIu16" new_shadow_doorbell %"PRIu16""
|
||||
pci_nvme_shadow_doorbell_sq(uint16_t sqid, uint16_t new_shadow_doorbell) "sqid %"PRIu16" new_shadow_doorbell %"PRIu16""
|
||||
pci_nvme_open_zone(uint64_t slba, uint32_t zone_idx, int all) "open zone, slba=%"PRIu64", idx=%"PRIu32", all=%"PRIi32""
|
||||
pci_nvme_close_zone(uint64_t slba, uint32_t zone_idx, int all) "close zone, slba=%"PRIu64", idx=%"PRIu32", all=%"PRIi32""
|
||||
pci_nvme_finish_zone(uint64_t slba, uint32_t zone_idx, int all) "finish zone, slba=%"PRIu64", idx=%"PRIu32", all=%"PRIi32""
|
||||
|
||||
@ -98,28 +98,28 @@ enum NvmeCapMask {
|
||||
#define NVME_CAP_PMRS(cap) (((cap) >> CAP_PMRS_SHIFT) & CAP_PMRS_MASK)
|
||||
#define NVME_CAP_CMBS(cap) (((cap) >> CAP_CMBS_SHIFT) & CAP_CMBS_MASK)
|
||||
|
||||
#define NVME_CAP_SET_MQES(cap, val) (cap |= (uint64_t)(val & CAP_MQES_MASK) \
|
||||
<< CAP_MQES_SHIFT)
|
||||
#define NVME_CAP_SET_CQR(cap, val) (cap |= (uint64_t)(val & CAP_CQR_MASK) \
|
||||
<< CAP_CQR_SHIFT)
|
||||
#define NVME_CAP_SET_AMS(cap, val) (cap |= (uint64_t)(val & CAP_AMS_MASK) \
|
||||
<< CAP_AMS_SHIFT)
|
||||
#define NVME_CAP_SET_TO(cap, val) (cap |= (uint64_t)(val & CAP_TO_MASK) \
|
||||
<< CAP_TO_SHIFT)
|
||||
#define NVME_CAP_SET_DSTRD(cap, val) (cap |= (uint64_t)(val & CAP_DSTRD_MASK) \
|
||||
<< CAP_DSTRD_SHIFT)
|
||||
#define NVME_CAP_SET_NSSRS(cap, val) (cap |= (uint64_t)(val & CAP_NSSRS_MASK) \
|
||||
<< CAP_NSSRS_SHIFT)
|
||||
#define NVME_CAP_SET_CSS(cap, val) (cap |= (uint64_t)(val & CAP_CSS_MASK) \
|
||||
<< CAP_CSS_SHIFT)
|
||||
#define NVME_CAP_SET_MPSMIN(cap, val) (cap |= (uint64_t)(val & CAP_MPSMIN_MASK)\
|
||||
<< CAP_MPSMIN_SHIFT)
|
||||
#define NVME_CAP_SET_MPSMAX(cap, val) (cap |= (uint64_t)(val & CAP_MPSMAX_MASK)\
|
||||
<< CAP_MPSMAX_SHIFT)
|
||||
#define NVME_CAP_SET_PMRS(cap, val) (cap |= (uint64_t)(val & CAP_PMRS_MASK) \
|
||||
<< CAP_PMRS_SHIFT)
|
||||
#define NVME_CAP_SET_CMBS(cap, val) (cap |= (uint64_t)(val & CAP_CMBS_MASK) \
|
||||
<< CAP_CMBS_SHIFT)
|
||||
#define NVME_CAP_SET_MQES(cap, val) \
|
||||
((cap) |= (uint64_t)((val) & CAP_MQES_MASK) << CAP_MQES_SHIFT)
|
||||
#define NVME_CAP_SET_CQR(cap, val) \
|
||||
((cap) |= (uint64_t)((val) & CAP_CQR_MASK) << CAP_CQR_SHIFT)
|
||||
#define NVME_CAP_SET_AMS(cap, val) \
|
||||
((cap) |= (uint64_t)((val) & CAP_AMS_MASK) << CAP_AMS_SHIFT)
|
||||
#define NVME_CAP_SET_TO(cap, val) \
|
||||
((cap) |= (uint64_t)((val) & CAP_TO_MASK) << CAP_TO_SHIFT)
|
||||
#define NVME_CAP_SET_DSTRD(cap, val) \
|
||||
((cap) |= (uint64_t)((val) & CAP_DSTRD_MASK) << CAP_DSTRD_SHIFT)
|
||||
#define NVME_CAP_SET_NSSRS(cap, val) \
|
||||
((cap) |= (uint64_t)((val) & CAP_NSSRS_MASK) << CAP_NSSRS_SHIFT)
|
||||
#define NVME_CAP_SET_CSS(cap, val) \
|
||||
((cap) |= (uint64_t)((val) & CAP_CSS_MASK) << CAP_CSS_SHIFT)
|
||||
#define NVME_CAP_SET_MPSMIN(cap, val) \
|
||||
((cap) |= (uint64_t)((val) & CAP_MPSMIN_MASK) << CAP_MPSMIN_SHIFT)
|
||||
#define NVME_CAP_SET_MPSMAX(cap, val) \
|
||||
((cap) |= (uint64_t)((val) & CAP_MPSMAX_MASK) << CAP_MPSMAX_SHIFT)
|
||||
#define NVME_CAP_SET_PMRS(cap, val) \
|
||||
((cap) |= (uint64_t)((val) & CAP_PMRS_MASK) << CAP_PMRS_SHIFT)
|
||||
#define NVME_CAP_SET_CMBS(cap, val) \
|
||||
((cap) |= (uint64_t)((val) & CAP_CMBS_MASK) << CAP_CMBS_SHIFT)
|
||||
|
||||
enum NvmeCapCss {
|
||||
NVME_CAP_CSS_NVM = 1 << 0,
|
||||
@ -596,6 +596,7 @@ enum NvmeAdminCommands {
|
||||
NVME_ADM_CMD_DOWNLOAD_FW = 0x11,
|
||||
NVME_ADM_CMD_NS_ATTACHMENT = 0x15,
|
||||
NVME_ADM_CMD_VIRT_MNGMT = 0x1c,
|
||||
NVME_ADM_CMD_DBBUF_CONFIG = 0x7c,
|
||||
NVME_ADM_CMD_FORMAT_NVM = 0x80,
|
||||
NVME_ADM_CMD_SECURITY_SEND = 0x81,
|
||||
NVME_ADM_CMD_SECURITY_RECV = 0x82,
|
||||
@ -1141,6 +1142,7 @@ enum NvmeIdCtrlOacs {
|
||||
NVME_OACS_FORMAT = 1 << 1,
|
||||
NVME_OACS_FW = 1 << 2,
|
||||
NVME_OACS_NS_MGMT = 1 << 3,
|
||||
NVME_OACS_DBBUF = 1 << 8,
|
||||
};
|
||||
|
||||
enum NvmeIdCtrlOncs {
|
||||
|
||||
Loading…
Reference in New Issue
Block a user