msf2: Microsemi Smartfusion2 System Register block
Added Sytem register block of Smartfusion2. This block has PLL registers which are accessed by guest. Signed-off-by: Subbaraya Sundeep <sundeep.lkml@gmail.com> Reviewed-by: Alistair Francis <alistair.francis@xilinx.com> Acked-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-id: 20170920201737.25723-3-f4bug@amsat.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Subbaraya Sundeep
Peter Maydell
parent
96401bad45
commit
0ee1e1f469
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@ -59,3 +59,4 @@ obj-$(CONFIG_HYPERV_TESTDEV) += hyperv_testdev.o
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obj-$(CONFIG_AUX) += auxbus.o
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obj-$(CONFIG_ASPEED_SOC) += aspeed_scu.o aspeed_sdmc.o
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obj-y += mmio_interface.o
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obj-$(CONFIG_MSF2) += msf2-sysreg.o
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@ -0,0 +1,160 @@
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/*
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* System Register block model of Microsemi SmartFusion2.
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*
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* Copyright (c) 2017 Subbaraya Sundeep <sundeep.lkml@gmail.com>
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version
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* 2 of the License, or (at your option) any later version.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, see <http://www.gnu.org/licenses/>.
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*/
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#include "qemu/osdep.h"
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#include "qapi/error.h"
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#include "qemu/log.h"
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#include "hw/misc/msf2-sysreg.h"
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#include "qemu/error-report.h"
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#include "trace.h"
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static inline int msf2_divbits(uint32_t div)
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{
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int r = ctz32(div);
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return (div < 8) ? r : r + 1;
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}
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static void msf2_sysreg_reset(DeviceState *d)
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{
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MSF2SysregState *s = MSF2_SYSREG(d);
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s->regs[MSSDDR_PLL_STATUS_LOW_CR] = 0x021A2358;
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s->regs[MSSDDR_PLL_STATUS] = 0x3;
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s->regs[MSSDDR_FACC1_CR] = msf2_divbits(s->apb0div) << 5 |
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msf2_divbits(s->apb1div) << 2;
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}
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static uint64_t msf2_sysreg_read(void *opaque, hwaddr offset,
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unsigned size)
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{
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MSF2SysregState *s = opaque;
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uint32_t ret = 0;
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offset >>= 2;
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if (offset < ARRAY_SIZE(s->regs)) {
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ret = s->regs[offset];
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trace_msf2_sysreg_read(offset << 2, ret);
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} else {
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qemu_log_mask(LOG_GUEST_ERROR,
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"%s: Bad offset 0x%08" HWADDR_PRIx "\n", __func__,
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offset << 2);
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}
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return ret;
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}
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static void msf2_sysreg_write(void *opaque, hwaddr offset,
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uint64_t val, unsigned size)
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{
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MSF2SysregState *s = opaque;
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uint32_t newval = val;
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offset >>= 2;
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switch (offset) {
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case MSSDDR_PLL_STATUS:
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trace_msf2_sysreg_write_pll_status();
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break;
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case ESRAM_CR:
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case DDR_CR:
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case ENVM_REMAP_BASE_CR:
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if (newval != s->regs[offset]) {
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qemu_log_mask(LOG_UNIMP,
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TYPE_MSF2_SYSREG": remapping not supported\n");
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}
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break;
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default:
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if (offset < ARRAY_SIZE(s->regs)) {
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trace_msf2_sysreg_write(offset << 2, newval, s->regs[offset]);
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s->regs[offset] = newval;
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} else {
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qemu_log_mask(LOG_GUEST_ERROR,
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"%s: Bad offset 0x%08" HWADDR_PRIx "\n", __func__,
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offset << 2);
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}
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break;
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}
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}
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static const MemoryRegionOps sysreg_ops = {
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.read = msf2_sysreg_read,
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.write = msf2_sysreg_write,
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.endianness = DEVICE_NATIVE_ENDIAN,
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};
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static void msf2_sysreg_init(Object *obj)
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{
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MSF2SysregState *s = MSF2_SYSREG(obj);
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memory_region_init_io(&s->iomem, obj, &sysreg_ops, s, TYPE_MSF2_SYSREG,
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MSF2_SYSREG_MMIO_SIZE);
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sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->iomem);
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}
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static const VMStateDescription vmstate_msf2_sysreg = {
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.name = TYPE_MSF2_SYSREG,
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.version_id = 1,
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.minimum_version_id = 1,
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.fields = (VMStateField[]) {
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VMSTATE_UINT32_ARRAY(regs, MSF2SysregState, MSF2_SYSREG_MMIO_SIZE / 4),
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VMSTATE_END_OF_LIST()
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}
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};
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static Property msf2_sysreg_properties[] = {
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/* default divisors in Libero GUI */
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DEFINE_PROP_UINT8("apb0divisor", MSF2SysregState, apb0div, 2),
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DEFINE_PROP_UINT8("apb1divisor", MSF2SysregState, apb1div, 2),
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DEFINE_PROP_END_OF_LIST(),
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};
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static void msf2_sysreg_realize(DeviceState *dev, Error **errp)
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{
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MSF2SysregState *s = MSF2_SYSREG(dev);
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if ((s->apb0div > 32 || !is_power_of_2(s->apb0div))
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|| (s->apb1div > 32 || !is_power_of_2(s->apb1div))) {
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error_setg(errp, "Invalid apb divisor value");
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error_append_hint(errp, "apb divisor must be a power of 2"
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" and maximum value is 32\n");
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}
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}
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static void msf2_sysreg_class_init(ObjectClass *klass, void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(klass);
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dc->vmsd = &vmstate_msf2_sysreg;
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dc->reset = msf2_sysreg_reset;
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dc->props = msf2_sysreg_properties;
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dc->realize = msf2_sysreg_realize;
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}
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static const TypeInfo msf2_sysreg_info = {
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.name = TYPE_MSF2_SYSREG,
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.parent = TYPE_SYS_BUS_DEVICE,
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.class_init = msf2_sysreg_class_init,
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.instance_size = sizeof(MSF2SysregState),
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.instance_init = msf2_sysreg_init,
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};
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static void msf2_sysreg_register_types(void)
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{
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type_register_static(&msf2_sysreg_info);
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}
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type_init(msf2_sysreg_register_types)
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@ -61,3 +61,8 @@ mps2_scc_reset(void) "MPS2 SCC: reset"
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mps2_scc_leds(char led7, char led6, char led5, char led4, char led3, char led2, char led1, char led0) "MPS2 SCC LEDs: %c%c%c%c%c%c%c%c"
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mps2_scc_cfg_write(unsigned function, unsigned device, uint32_t value) "MPS2 SCC config write: function %d device %d data 0x%" PRIx32
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mps2_scc_cfg_read(unsigned function, unsigned device, uint32_t value) "MPS2 SCC config read: function %d device %d data 0x%" PRIx32
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# hw/misc/msf2-sysreg.c
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msf2_sysreg_write(uint64_t offset, uint32_t val, uint32_t prev) "msf2-sysreg write: addr 0x%08" HWADDR_PRIx " data 0x%" PRIx32 " prev 0x%" PRIx32
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msf2_sysreg_read(uint64_t offset, uint32_t val) "msf2-sysreg read: addr 0x%08" HWADDR_PRIx " data 0x%08" PRIx32
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msf2_sysreg_write_pll_status(void) "Invalid write to read only PLL status register"
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@ -0,0 +1,77 @@
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/*
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* Microsemi SmartFusion2 SYSREG
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*
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* Copyright (c) 2017 Subbaraya Sundeep <sundeep.lkml@gmail.com>
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#ifndef HW_MSF2_SYSREG_H
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#define HW_MSF2_SYSREG_H
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#include "hw/sysbus.h"
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enum {
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ESRAM_CR = 0x00 / 4,
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ESRAM_MAX_LAT,
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DDR_CR,
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ENVM_CR,
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ENVM_REMAP_BASE_CR,
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ENVM_REMAP_FAB_CR,
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CC_CR,
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CC_REGION_CR,
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CC_LOCK_BASE_ADDR_CR,
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CC_FLUSH_INDX_CR,
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DDRB_BUF_TIMER_CR,
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DDRB_NB_ADDR_CR,
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DDRB_NB_SIZE_CR,
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DDRB_CR,
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SOFT_RESET_CR = 0x48 / 4,
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M3_CR,
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GPIO_SYSRESET_SEL_CR = 0x58 / 4,
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MDDR_CR = 0x60 / 4,
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MSSDDR_PLL_STATUS_LOW_CR = 0x90 / 4,
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MSSDDR_PLL_STATUS_HIGH_CR,
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MSSDDR_FACC1_CR,
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MSSDDR_FACC2_CR,
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MSSDDR_PLL_STATUS = 0x150 / 4,
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};
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#define MSF2_SYSREG_MMIO_SIZE 0x300
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#define TYPE_MSF2_SYSREG "msf2-sysreg"
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#define MSF2_SYSREG(obj) OBJECT_CHECK(MSF2SysregState, (obj), TYPE_MSF2_SYSREG)
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typedef struct MSF2SysregState {
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SysBusDevice parent_obj;
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MemoryRegion iomem;
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uint8_t apb0div;
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uint8_t apb1div;
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uint32_t regs[MSF2_SYSREG_MMIO_SIZE / 4];
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} MSF2SysregState;
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#endif /* HW_MSF2_SYSREG_H */
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