From 0ee342256af9205e7388efdf193a6d8f1ba1a617 Mon Sep 17 00:00:00 2001 From: Bin Meng Date: Tue, 28 Feb 2023 18:40:19 +0800 Subject: [PATCH] target/riscv: Use g_assert() for the predicate() NULL check At present riscv_csrrw_check() checks the CSR predicate() against NULL and throws RISCV_EXCP_ILLEGAL_INST if it is NULL. But this is a pure software check, and has nothing to do with the emulation of the hardware behavior, thus it is inappropriate to return illegal instruction exception when software forgets to install the hook. Change to use g_assert() instead. Signed-off-by: Bin Meng Reviewed-by: Weiwei Li Message-ID: <20230228104035.1879882-4-bmeng@tinylab.org> Signed-off-by: Palmer Dabbelt --- target/riscv/csr.c | 6 +----- 1 file changed, 1 insertion(+), 5 deletions(-) diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 4cc2c6370f..cfd7ffc5c2 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -3786,11 +3786,6 @@ static inline RISCVException riscv_csrrw_check(CPURISCVState *env, return RISCV_EXCP_ILLEGAL_INST; } - /* check predicate */ - if (!csr_ops[csrno].predicate) { - return RISCV_EXCP_ILLEGAL_INST; - } - /* read / write check */ if (write_mask && read_only) { return RISCV_EXCP_ILLEGAL_INST; @@ -3803,6 +3798,7 @@ static inline RISCVException riscv_csrrw_check(CPURISCVState *env, * illegal instruction exception should be triggered instead of virtual * instruction exception. Hence this comes after the read / write check. */ + g_assert(csr_ops[csrno].predicate != NULL); RISCVException ret = csr_ops[csrno].predicate(env, csrno); if (ret != RISCV_EXCP_NONE) { return ret;