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hw/misc: Add Microchip PolarFire SoC SYSREG module support 

This creates a minimum model for Microchip PolarFire SoC SYSREG
module. It only implements the ENVM_CR register to tell guest
software that eNVM is running at the configured divider rate.

Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 1603863010-15807-7-git-send-email-bmeng.cn@gmail.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
This commit is contained in:
Bin Meng 2020-10-28 13:30:06 +08:00 committed by Alistair Francis
parent e35d617919
commit 0f25065cb6
5 changed files with 144 additions and 0 deletions
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2
MAINTAINERS
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@ -1329,10 +1329,12 @@ F: hw/riscv/microchip_pfsoc.c
F: hw/char/mchp_pfsoc_mmuart.c
F: hw/misc/mchp_pfsoc_dmc.c
F: hw/misc/mchp_pfsoc_ioscb.c
F: hw/misc/mchp_pfsoc_sysreg.c
F: include/hw/riscv/microchip_pfsoc.h
F: include/hw/char/mchp_pfsoc_mmuart.h
F: include/hw/misc/mchp_pfsoc_dmc.h
F: include/hw/misc/mchp_pfsoc_ioscb.h
F: include/hw/misc/mchp_pfsoc_sysreg.h
RX Machines
-----------

3
hw/misc/Kconfig
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@ -145,6 +145,9 @@ config MCHP_PFSOC_DMC
config MCHP_PFSOC_IOSCB
bool
config MCHP_PFSOC_SYSREG
bool
config SIFIVE_TEST
bool

99
hw/misc/mchp_pfsoc_sysreg.c Normal file
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@ -0,0 +1,99 @@
/*
* Microchip PolarFire SoC SYSREG module emulation
*
* Copyright (c) 2020 Wind River Systems, Inc.
*
* Author:
* Bin Meng <bin.meng@windriver.com>
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 or
* (at your option) version 3 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, see <http://www.gnu.org/licenses/>.
*/
#include "qemu/osdep.h"
#include "qemu/bitops.h"
#include "qemu/log.h"
#include "qapi/error.h"
#include "hw/hw.h"
#include "hw/sysbus.h"
#include "hw/misc/mchp_pfsoc_sysreg.h"
#define ENVM_CR 0xb8
static uint64_t mchp_pfsoc_sysreg_read(void *opaque, hwaddr offset,
unsigned size)
{
uint32_t val = 0;
switch (offset) {
case ENVM_CR:
/* Indicate the eNVM is running at the configured divider rate */
val = BIT(6);
break;
default:
qemu_log_mask(LOG_UNIMP, "%s: unimplemented device read "
"(size %d, offset 0x%" HWADDR_PRIx ")\n",
__func__, size, offset);
break;
}
return val;
}
static void mchp_pfsoc_sysreg_write(void *opaque, hwaddr offset,
uint64_t value, unsigned size)
{
qemu_log_mask(LOG_UNIMP, "%s: unimplemented device write "
"(size %d, value 0x%" PRIx64
", offset 0x%" HWADDR_PRIx ")\n",
__func__, size, value, offset);
}
static const MemoryRegionOps mchp_pfsoc_sysreg_ops = {
.read = mchp_pfsoc_sysreg_read,
.write = mchp_pfsoc_sysreg_write,
.endianness = DEVICE_LITTLE_ENDIAN,
};
static void mchp_pfsoc_sysreg_realize(DeviceState *dev, Error **errp)
{
MchpPfSoCSysregState *s = MCHP_PFSOC_SYSREG(dev);
memory_region_init_io(&s->sysreg, OBJECT(dev),
&mchp_pfsoc_sysreg_ops, s,
"mchp.pfsoc.sysreg",
MCHP_PFSOC_SYSREG_REG_SIZE);
sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->sysreg);
}
static void mchp_pfsoc_sysreg_class_init(ObjectClass *klass, void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
dc->desc = "Microchip PolarFire SoC SYSREG module";
dc->realize = mchp_pfsoc_sysreg_realize;
}
static const TypeInfo mchp_pfsoc_sysreg_info = {
.name = TYPE_MCHP_PFSOC_SYSREG,
.parent = TYPE_SYS_BUS_DEVICE,
.instance_size = sizeof(MchpPfSoCSysregState),
.class_init = mchp_pfsoc_sysreg_class_init,
};
static void mchp_pfsoc_sysreg_register_types(void)
{
type_register_static(&mchp_pfsoc_sysreg_info);
}
type_init(mchp_pfsoc_sysreg_register_types)

1
hw/misc/meson.build
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@ -25,6 +25,7 @@ softmmu_ss.add(when: 'CONFIG_MOS6522', if_true: files('mos6522.c'))
# RISC-V devices
softmmu_ss.add(when: 'CONFIG_MCHP_PFSOC_DMC', if_true: files('mchp_pfsoc_dmc.c'))
softmmu_ss.add(when: 'CONFIG_MCHP_PFSOC_IOSCB', if_true: files('mchp_pfsoc_ioscb.c'))
softmmu_ss.add(when: 'CONFIG_MCHP_PFSOC_SYSREG', if_true: files('mchp_pfsoc_sysreg.c'))
softmmu_ss.add(when: 'CONFIG_SIFIVE_TEST', if_true: files('sifive_test.c'))
softmmu_ss.add(when: 'CONFIG_SIFIVE_E_PRCI', if_true: files('sifive_e_prci.c'))
softmmu_ss.add(when: 'CONFIG_SIFIVE_U_OTP', if_true: files('sifive_u_otp.c'))

39
include/hw/misc/mchp_pfsoc_sysreg.h Normal file
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@ -0,0 +1,39 @@
/*
* Microchip PolarFire SoC SYSREG module emulation
*
* Copyright (c) 2020 Wind River Systems, Inc.
*
* Author:
* Bin Meng <bin.meng@windriver.com>
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 or
* (at your option) version 3 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, see <http://www.gnu.org/licenses/>.
*/
#ifndef MCHP_PFSOC_SYSREG_H
#define MCHP_PFSOC_SYSREG_H
#define MCHP_PFSOC_SYSREG_REG_SIZE 0x2000
typedef struct MchpPfSoCSysregState {
SysBusDevice parent;
MemoryRegion sysreg;
} MchpPfSoCSysregState;
#define TYPE_MCHP_PFSOC_SYSREG "mchp.pfsoc.sysreg"
#define MCHP_PFSOC_SYSREG(obj) \
OBJECT_CHECK(MchpPfSoCSysregState, (obj), \
TYPE_MCHP_PFSOC_SYSREG)
#endif /* MCHP_PFSOC_SYSREG_H */