target/arm: Implement HCR_EL2.TTLBIS traps
For FEAT_EVT, the HCR_EL2.TTLBIS bit allows trapping on EL1 use of TLB maintenance instructions that operate on the inner shareable domain: AArch64: TLBI VMALLE1IS, TLBI VAE1IS, TLBI ASIDE1IS, TLBI VAAE1IS, TLBI VALE1IS, TLBI VAALE1IS, TLBI RVAE1IS, TLBI RVAAE1IS, TLBI RVALE1IS, and TLBI RVAALE1IS. AArch32: TLBIALLIS, TLBIMVAIS, TLBIASIDIS, TLBIMVAAIS, TLBIMVALIS, and TLBIMVAALIS. Add the trapping support. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
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@ -362,6 +362,17 @@ static CPAccessResult access_ttlb(CPUARMState *env, const ARMCPRegInfo *ri,
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return CP_ACCESS_OK;
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}
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/* Check for traps from EL1 due to HCR_EL2.TTLB or TTLBIS. */
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static CPAccessResult access_ttlbis(CPUARMState *env, const ARMCPRegInfo *ri,
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bool isread)
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{
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if (arm_current_el(env) == 1 &&
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(arm_hcr_el2_eff(env) & (HCR_TTLB | HCR_TTLBIS))) {
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return CP_ACCESS_TRAP_EL2;
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}
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return CP_ACCESS_OK;
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}
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static void dacr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
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{
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ARMCPU *cpu = env_archcpu(env);
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@ -2206,16 +2217,16 @@ static const ARMCPRegInfo v7_cp_reginfo[] = {
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static const ARMCPRegInfo v7mp_cp_reginfo[] = {
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/* 32 bit TLB invalidates, Inner Shareable */
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{ .name = "TLBIALLIS", .cp = 15, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 0,
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.type = ARM_CP_NO_RAW, .access = PL1_W, .accessfn = access_ttlb,
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.type = ARM_CP_NO_RAW, .access = PL1_W, .accessfn = access_ttlbis,
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.writefn = tlbiall_is_write },
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{ .name = "TLBIMVAIS", .cp = 15, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 1,
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.type = ARM_CP_NO_RAW, .access = PL1_W, .accessfn = access_ttlb,
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.type = ARM_CP_NO_RAW, .access = PL1_W, .accessfn = access_ttlbis,
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.writefn = tlbimva_is_write },
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{ .name = "TLBIASIDIS", .cp = 15, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 2,
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.type = ARM_CP_NO_RAW, .access = PL1_W, .accessfn = access_ttlb,
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.type = ARM_CP_NO_RAW, .access = PL1_W, .accessfn = access_ttlbis,
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.writefn = tlbiasid_is_write },
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{ .name = "TLBIMVAAIS", .cp = 15, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 3,
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.type = ARM_CP_NO_RAW, .access = PL1_W, .accessfn = access_ttlb,
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.type = ARM_CP_NO_RAW, .access = PL1_W, .accessfn = access_ttlbis,
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.writefn = tlbimvaa_is_write },
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};
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@ -4948,27 +4959,27 @@ static const ARMCPRegInfo v8_cp_reginfo[] = {
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/* TLBI operations */
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{ .name = "TLBI_VMALLE1IS", .state = ARM_CP_STATE_AA64,
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.opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 0,
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.access = PL1_W, .accessfn = access_ttlb, .type = ARM_CP_NO_RAW,
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.access = PL1_W, .accessfn = access_ttlbis, .type = ARM_CP_NO_RAW,
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.writefn = tlbi_aa64_vmalle1is_write },
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{ .name = "TLBI_VAE1IS", .state = ARM_CP_STATE_AA64,
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.opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 1,
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.access = PL1_W, .accessfn = access_ttlb, .type = ARM_CP_NO_RAW,
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.access = PL1_W, .accessfn = access_ttlbis, .type = ARM_CP_NO_RAW,
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.writefn = tlbi_aa64_vae1is_write },
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{ .name = "TLBI_ASIDE1IS", .state = ARM_CP_STATE_AA64,
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.opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 2,
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.access = PL1_W, .accessfn = access_ttlb, .type = ARM_CP_NO_RAW,
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.access = PL1_W, .accessfn = access_ttlbis, .type = ARM_CP_NO_RAW,
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.writefn = tlbi_aa64_vmalle1is_write },
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{ .name = "TLBI_VAAE1IS", .state = ARM_CP_STATE_AA64,
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.opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 3,
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.access = PL1_W, .accessfn = access_ttlb, .type = ARM_CP_NO_RAW,
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.access = PL1_W, .accessfn = access_ttlbis, .type = ARM_CP_NO_RAW,
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.writefn = tlbi_aa64_vae1is_write },
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{ .name = "TLBI_VALE1IS", .state = ARM_CP_STATE_AA64,
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.opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 5,
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.access = PL1_W, .accessfn = access_ttlb, .type = ARM_CP_NO_RAW,
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.access = PL1_W, .accessfn = access_ttlbis, .type = ARM_CP_NO_RAW,
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.writefn = tlbi_aa64_vae1is_write },
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{ .name = "TLBI_VAALE1IS", .state = ARM_CP_STATE_AA64,
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.opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 7,
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.access = PL1_W, .accessfn = access_ttlb, .type = ARM_CP_NO_RAW,
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.access = PL1_W, .accessfn = access_ttlbis, .type = ARM_CP_NO_RAW,
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.writefn = tlbi_aa64_vae1is_write },
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{ .name = "TLBI_VMALLE1", .state = ARM_CP_STATE_AA64,
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.opc0 = 1, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 0,
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@ -5078,10 +5089,10 @@ static const ARMCPRegInfo v8_cp_reginfo[] = {
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#endif
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/* TLB invalidate last level of translation table walk */
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{ .name = "TLBIMVALIS", .cp = 15, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 5,
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.type = ARM_CP_NO_RAW, .access = PL1_W, .accessfn = access_ttlb,
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.type = ARM_CP_NO_RAW, .access = PL1_W, .accessfn = access_ttlbis,
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.writefn = tlbimva_is_write },
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{ .name = "TLBIMVAALIS", .cp = 15, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 7,
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.type = ARM_CP_NO_RAW, .access = PL1_W, .accessfn = access_ttlb,
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.type = ARM_CP_NO_RAW, .access = PL1_W, .accessfn = access_ttlbis,
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.writefn = tlbimvaa_is_write },
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{ .name = "TLBIMVAL", .cp = 15, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 5,
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.type = ARM_CP_NO_RAW, .access = PL1_W, .accessfn = access_ttlb,
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@ -6726,19 +6737,19 @@ static const ARMCPRegInfo pauth_reginfo[] = {
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static const ARMCPRegInfo tlbirange_reginfo[] = {
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{ .name = "TLBI_RVAE1IS", .state = ARM_CP_STATE_AA64,
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.opc0 = 1, .opc1 = 0, .crn = 8, .crm = 2, .opc2 = 1,
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.access = PL1_W, .accessfn = access_ttlb, .type = ARM_CP_NO_RAW,
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.access = PL1_W, .accessfn = access_ttlbis, .type = ARM_CP_NO_RAW,
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.writefn = tlbi_aa64_rvae1is_write },
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{ .name = "TLBI_RVAAE1IS", .state = ARM_CP_STATE_AA64,
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.opc0 = 1, .opc1 = 0, .crn = 8, .crm = 2, .opc2 = 3,
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.access = PL1_W, .accessfn = access_ttlb, .type = ARM_CP_NO_RAW,
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.access = PL1_W, .accessfn = access_ttlbis, .type = ARM_CP_NO_RAW,
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.writefn = tlbi_aa64_rvae1is_write },
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{ .name = "TLBI_RVALE1IS", .state = ARM_CP_STATE_AA64,
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.opc0 = 1, .opc1 = 0, .crn = 8, .crm = 2, .opc2 = 5,
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.access = PL1_W, .accessfn = access_ttlb, .type = ARM_CP_NO_RAW,
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.access = PL1_W, .accessfn = access_ttlbis, .type = ARM_CP_NO_RAW,
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.writefn = tlbi_aa64_rvae1is_write },
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{ .name = "TLBI_RVAALE1IS", .state = ARM_CP_STATE_AA64,
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.opc0 = 1, .opc1 = 0, .crn = 8, .crm = 2, .opc2 = 7,
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.access = PL1_W, .accessfn = access_ttlb, .type = ARM_CP_NO_RAW,
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.access = PL1_W, .accessfn = access_ttlbis, .type = ARM_CP_NO_RAW,
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.writefn = tlbi_aa64_rvae1is_write },
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{ .name = "TLBI_RVAE1OS", .state = ARM_CP_STATE_AA64,
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.opc0 = 1, .opc1 = 0, .crn = 8, .crm = 5, .opc2 = 1,
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