target/arm: Convert Neon 3-reg-diff narrowing ops to decodetree
Convert the narrow-to-high-half insns VADDHN, VSUBHN, VRADDHN, VRSUBHN in the Neon 3-registers-different-lengths group to decodetree. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
This commit is contained in:
Peter Maydell
parent
b28be09570
commit
0fa1ab0302
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@ -438,5 +438,11 @@ Vimm_1r 1111 001 . 1 . 000 ... .... cmode:4 0 . op:1 1 .... @1reg_imm
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VSUBW_S_3d 1111 001 0 1 . .. .... .... 0011 . 0 . 0 .... @3diff
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VSUBW_U_3d 1111 001 1 1 . .. .... .... 0011 . 0 . 0 .... @3diff
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VADDHN_3d 1111 001 0 1 . .. .... .... 0100 . 0 . 0 .... @3diff
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VRADDHN_3d 1111 001 1 1 . .. .... .... 0100 . 0 . 0 .... @3diff
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VSUBHN_3d 1111 001 0 1 . .. .... .... 0110 . 0 . 0 .... @3diff
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VRSUBHN_3d 1111 001 1 1 . .. .... .... 0110 . 0 . 0 .... @3diff
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]
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}
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@ -1932,3 +1932,90 @@ DO_PREWIDEN(VADDW_S, s, ext, add, true)
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DO_PREWIDEN(VADDW_U, u, extu, add, true)
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DO_PREWIDEN(VSUBW_S, s, ext, sub, true)
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DO_PREWIDEN(VSUBW_U, u, extu, sub, true)
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static bool do_narrow_3d(DisasContext *s, arg_3diff *a,
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NeonGenTwo64OpFn *opfn, NeonGenNarrowFn *narrowfn)
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{
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/* 3-regs different lengths, narrowing (VADDHN/VSUBHN/VRADDHN/VRSUBHN) */
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TCGv_i64 rn_64, rm_64;
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TCGv_i32 rd0, rd1;
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if (!arm_dc_feature(s, ARM_FEATURE_NEON)) {
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return false;
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}
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/* UNDEF accesses to D16-D31 if they don't exist. */
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if (!dc_isar_feature(aa32_simd_r32, s) &&
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((a->vd | a->vn | a->vm) & 0x10)) {
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return false;
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}
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if (!opfn || !narrowfn) {
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/* size == 3 case, which is an entirely different insn group */
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return false;
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}
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if ((a->vn | a->vm) & 1) {
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return false;
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}
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if (!vfp_access_check(s)) {
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return true;
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}
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rn_64 = tcg_temp_new_i64();
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rm_64 = tcg_temp_new_i64();
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rd0 = tcg_temp_new_i32();
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rd1 = tcg_temp_new_i32();
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neon_load_reg64(rn_64, a->vn);
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neon_load_reg64(rm_64, a->vm);
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opfn(rn_64, rn_64, rm_64);
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narrowfn(rd0, rn_64);
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neon_load_reg64(rn_64, a->vn + 1);
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neon_load_reg64(rm_64, a->vm + 1);
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opfn(rn_64, rn_64, rm_64);
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narrowfn(rd1, rn_64);
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neon_store_reg(a->vd, 0, rd0);
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neon_store_reg(a->vd, 1, rd1);
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tcg_temp_free_i64(rn_64);
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tcg_temp_free_i64(rm_64);
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return true;
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}
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#define DO_NARROW_3D(INSN, OP, NARROWTYPE, EXTOP) \
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static bool trans_##INSN##_3d(DisasContext *s, arg_3diff *a) \
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{ \
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static NeonGenTwo64OpFn * const addfn[] = { \
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gen_helper_neon_##OP##l_u16, \
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gen_helper_neon_##OP##l_u32, \
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tcg_gen_##OP##_i64, \
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NULL, \
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}; \
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static NeonGenNarrowFn * const narrowfn[] = { \
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gen_helper_neon_##NARROWTYPE##_high_u8, \
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gen_helper_neon_##NARROWTYPE##_high_u16, \
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EXTOP, \
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NULL, \
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}; \
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return do_narrow_3d(s, a, addfn[a->size], narrowfn[a->size]); \
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}
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static void gen_narrow_round_high_u32(TCGv_i32 rd, TCGv_i64 rn)
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{
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tcg_gen_addi_i64(rn, rn, 1u << 31);
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tcg_gen_extrh_i64_i32(rd, rn);
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}
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DO_NARROW_3D(VADDHN, add, narrow, tcg_gen_extrh_i64_i32)
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DO_NARROW_3D(VSUBHN, sub, narrow, tcg_gen_extrh_i64_i32)
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DO_NARROW_3D(VRADDHN, add, narrow_round, gen_narrow_round_high_u32)
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DO_NARROW_3D(VRSUBHN, sub, narrow_round, gen_narrow_round_high_u32)
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@ -3231,16 +3231,6 @@ static inline void gen_neon_addl(int size)
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}
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}
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static inline void gen_neon_subl(int size)
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{
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switch (size) {
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case 0: gen_helper_neon_subl_u16(CPU_V001); break;
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case 1: gen_helper_neon_subl_u32(CPU_V001); break;
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case 2: tcg_gen_sub_i64(CPU_V001); break;
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default: abort();
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}
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}
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static inline void gen_neon_negl(TCGv_i64 var, int size)
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{
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switch (size) {
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@ -5239,8 +5229,6 @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
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op = (insn >> 8) & 0xf;
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if ((insn & (1 << 6)) == 0) {
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/* Three registers of different lengths. */
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int src1_wide;
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int src2_wide;
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/* undefreq: bit 0 : UNDEF if size == 0
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* bit 1 : UNDEF if size == 1
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* bit 2 : UNDEF if size == 2
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@ -5254,9 +5242,9 @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
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{0, 0, 0, 7}, /* VADDW: handled by decodetree */
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{0, 0, 0, 7}, /* VSUBL: handled by decodetree */
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{0, 0, 0, 7}, /* VSUBW: handled by decodetree */
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{0, 1, 1, 0}, /* VADDHN */
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{0, 0, 0, 7}, /* VADDHN: handled by decodetree */
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{0, 0, 0, 0}, /* VABAL */
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{0, 1, 1, 0}, /* VSUBHN */
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{0, 0, 0, 7}, /* VSUBHN: handled by decodetree */
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{0, 0, 0, 0}, /* VABDL */
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{0, 0, 0, 0}, /* VMLAL */
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{0, 0, 0, 9}, /* VQDMLAL */
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@ -5268,17 +5256,13 @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
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{0, 0, 0, 7}, /* Reserved: always UNDEF */
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};
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src1_wide = neon_3reg_wide[op][1];
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src2_wide = neon_3reg_wide[op][2];
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undefreq = neon_3reg_wide[op][3];
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if ((undefreq & (1 << size)) ||
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((undefreq & 8) && u)) {
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return 1;
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}
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if ((src1_wide && (rn & 1)) ||
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(src2_wide && (rm & 1)) ||
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(!src2_wide && (rd & 1))) {
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if (rd & 1) {
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return 1;
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}
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@ -5302,42 +5286,26 @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
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/* Avoid overlapping operands. Wide source operands are
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always aligned so will never overlap with wide
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destinations in problematic ways. */
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if (rd == rm && !src2_wide) {
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if (rd == rm) {
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tmp = neon_load_reg(rm, 1);
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neon_store_scratch(2, tmp);
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} else if (rd == rn && !src1_wide) {
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} else if (rd == rn) {
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tmp = neon_load_reg(rn, 1);
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neon_store_scratch(2, tmp);
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}
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tmp3 = NULL;
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for (pass = 0; pass < 2; pass++) {
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if (src1_wide) {
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neon_load_reg64(cpu_V0, rn + pass);
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tmp = NULL;
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if (pass == 1 && rd == rn) {
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tmp = neon_load_scratch(2);
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} else {
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if (pass == 1 && rd == rn) {
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tmp = neon_load_scratch(2);
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} else {
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tmp = neon_load_reg(rn, pass);
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}
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tmp = neon_load_reg(rn, pass);
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}
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if (src2_wide) {
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neon_load_reg64(cpu_V1, rm + pass);
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tmp2 = NULL;
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if (pass == 1 && rd == rm) {
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tmp2 = neon_load_scratch(2);
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} else {
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if (pass == 1 && rd == rm) {
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tmp2 = neon_load_scratch(2);
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} else {
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tmp2 = neon_load_reg(rm, pass);
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}
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tmp2 = neon_load_reg(rm, pass);
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}
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switch (op) {
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case 0: case 1: case 4: /* VADDL, VADDW, VADDHN, VRADDHN */
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gen_neon_addl(size);
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break;
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case 2: case 3: case 6: /* VSUBL, VSUBW, VSUBHN, VRSUBHN */
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gen_neon_subl(size);
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break;
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case 5: case 7: /* VABAL, VABDL */
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switch ((size << 1) | u) {
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case 0:
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@ -5395,43 +5363,6 @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
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abort();
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}
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neon_store_reg64(cpu_V0, rd + pass);
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} else if (op == 4 || op == 6) {
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/* Narrowing operation. */
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tmp = tcg_temp_new_i32();
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if (!u) {
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switch (size) {
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case 0:
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gen_helper_neon_narrow_high_u8(tmp, cpu_V0);
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break;
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case 1:
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gen_helper_neon_narrow_high_u16(tmp, cpu_V0);
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break;
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case 2:
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tcg_gen_extrh_i64_i32(tmp, cpu_V0);
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break;
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default: abort();
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}
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} else {
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switch (size) {
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case 0:
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gen_helper_neon_narrow_round_high_u8(tmp, cpu_V0);
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break;
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case 1:
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gen_helper_neon_narrow_round_high_u16(tmp, cpu_V0);
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break;
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case 2:
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tcg_gen_addi_i64(cpu_V0, cpu_V0, 1u << 31);
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tcg_gen_extrh_i64_i32(tmp, cpu_V0);
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break;
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default: abort();
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}
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}
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if (pass == 0) {
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tmp3 = tmp;
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} else {
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neon_store_reg(rd, 0, tmp3);
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neon_store_reg(rd, 1, tmp);
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}
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} else {
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/* Write back the result. */
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neon_store_reg64(cpu_V0, rd + pass);
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