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target/arm: Implement MVE VCADD 

Implement the MVE VCADD insn.  Note that here the size bit is the
opposite sense to the other 2-operand fp insns.

We don't check for the sz == 1 && Qd == Qm UNPREDICTABLE case,
because that would mean we can't use the DO_2OP_FP macro in
translate-mve.c.

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Peter Maydell 2021-09-01 09:02:35 +01:00
parent 82af0153d3
commit 104afc68cf
4 changed files with 57 additions and 1 deletions
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6
target/arm/helper-mve.h
View File

@ -428,6 +428,12 @@ DEF_HELPER_FLAGS_4(mve_vmaxnms, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr)
DEF_HELPER_FLAGS_4(mve_vminnmh, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr)
DEF_HELPER_FLAGS_4(mve_vminnms, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr)
DEF_HELPER_FLAGS_4(mve_vfcadd90h, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr)
DEF_HELPER_FLAGS_4(mve_vfcadd90s, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr)
DEF_HELPER_FLAGS_4(mve_vfcadd270h, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr)
DEF_HELPER_FLAGS_4(mve_vfcadd270s, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr)
DEF_HELPER_FLAGS_4(mve_vadd_scalarb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
DEF_HELPER_FLAGS_4(mve_vadd_scalarh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
DEF_HELPER_FLAGS_4(mve_vadd_scalarw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)

8
target/arm/mve.decode
View File

@ -29,6 +29,8 @@
# 2 operand fp insns have size in bit 20: 1 for 16 bit, 0 for 32 bit,
# like Neon FP insns.
%2op_fp_size 20:1 !function=neon_3same_fp_size
# VCADD is an exception, where bit 20 is 0 for 16 bit and 1 for 32 bit
%2op_fp_size_rev 20:1 !function=plus_1
# 1imm format immediate
%imm_28_16_0 28:1 16:3 0:4
@ -125,6 +127,9 @@
@2op_fp .... .... .... .... .... .... .... .... &2op \
qd=%qd qn=%qn qm=%qm size=%2op_fp_size
@2op_fp_size_rev .... .... .... .... .... .... .... .... &2op \
qd=%qd qn=%qn qm=%qm size=%2op_fp_size_rev
# Vector loads and stores
# Widening loads and narrowing stores:
@ -631,3 +636,6 @@ VABD_fp 1111 1111 0 . 1 . ... 0 ... 0 1101 . 1 . 0 ... 0 @2op_fp
VMAXNM 1111 1111 0 . 0 . ... 0 ... 0 1111 . 1 . 1 ... 0 @2op_fp
VMINNM 1111 1111 0 . 1 . ... 0 ... 0 1111 . 1 . 1 ... 0 @2op_fp
VCADD90_fp 1111 1100 1 . 0 . ... 0 ... 0 1000 . 1 . 0 ... 0 @2op_fp_size_rev
VCADD270_fp 1111 1101 1 . 0 . ... 0 ... 0 1000 . 1 . 0 ... 0 @2op_fp_size_rev

40
target/arm/mve_helper.c
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@ -2854,3 +2854,43 @@ static inline float32 float32_abd(float32 a, float32 b, float_status *s)
DO_2OP_FP_ALL(vfabd, abd)
DO_2OP_FP_ALL(vmaxnm, maxnum)
DO_2OP_FP_ALL(vminnm, minnum)
#define DO_VCADD_FP(OP, ESIZE, TYPE, FN0, FN1) \
void HELPER(glue(mve_, OP))(CPUARMState *env, \
void *vd, void *vn, void *vm) \
{ \
TYPE *d = vd, *n = vn, *m = vm; \
TYPE r[16 / ESIZE]; \
uint16_t tm, mask = mve_element_mask(env); \
unsigned e; \
float_status *fpst; \
float_status scratch_fpst; \
/* Calculate all results first to avoid overwriting inputs */ \
for (e = 0, tm = mask; e < 16 / ESIZE; e++, tm >>= ESIZE) { \
if ((tm & MAKE_64BIT_MASK(0, ESIZE)) == 0) { \
r[e] = 0; \
continue; \
} \
fpst = (ESIZE == 2) ? &env->vfp.standard_fp_status_f16 : \
&env->vfp.standard_fp_status; \
if (!(tm & 1)) { \
/* We need the result but without updating flags */ \
scratch_fpst = *fpst; \
fpst = &scratch_fpst; \
} \
if (!(e & 1)) { \
r[e] = FN0(n[H##ESIZE(e)], m[H##ESIZE(e + 1)], fpst); \
} else { \
r[e] = FN1(n[H##ESIZE(e)], m[H##ESIZE(e - 1)], fpst); \
} \
} \
for (e = 0; e < 16 / ESIZE; e++, mask >>= ESIZE) { \
mergemask(&d[H##ESIZE(e)], r[e], mask); \
} \
mve_advance_vpt(env); \
}
DO_VCADD_FP(vfcadd90h, 2, float16, float16_sub, float16_add)
DO_VCADD_FP(vfcadd90s, 4, float32, float32_sub, float32_add)
DO_VCADD_FP(vfcadd270h, 2, float16, float16_add, float16_sub)
DO_VCADD_FP(vfcadd270s, 4, float32, float32_add, float32_sub)

4
target/arm/translate-mve.c
View File

@ -852,6 +852,8 @@ DO_2OP_FP(VMUL_fp, vfmul)
DO_2OP_FP(VABD_fp, vfabd)
DO_2OP_FP(VMAXNM, vmaxnm)
DO_2OP_FP(VMINNM, vminnm)
DO_2OP_FP(VCADD90_fp, vfcadd90)
DO_2OP_FP(VCADD270_fp, vfcadd270)
static bool do_2op_scalar(DisasContext *s, arg_2scalar *a,
MVEGenTwoOpScalarFn fn)
@ -883,7 +885,7 @@ static bool do_2op_scalar(DisasContext *s, arg_2scalar *a,
return true;
}
#define DO_2OP_SCALAR(INSN, FN) \
#define DO_2OP_SCALAR(INSN, FN) \
static bool trans_##INSN(DisasContext *s, arg_2scalar *a) \
{ \
static MVEGenTwoOpScalarFn * const fns[] = { \