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hw/block/nvme: move device parameters to separate struct 

Move device configuration parameters to separate struct to make it
explicit what is configurable and what is set internally.

Signed-off-by: Klaus Jensen <klaus.jensen@cnexlabs.com>
Signed-off-by: Klaus Jensen <k.jensen@samsung.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Reviewed-by: Maxim Levitsky <mlevitsk@redhat.com>
Message-Id: <20200609190333.59390-5-its@irrelevant.dk>
Signed-off-by: Kevin Wolf <kwolf@redhat.com>
This commit is contained in:
Klaus Jensen 2020-06-09 21:03:15 +02:00 committed by Kevin Wolf
parent 4920786ee6
commit 1065abfbf1
2 changed files with 34 additions and 26 deletions
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49
hw/block/nvme.c
View File

@ -77,12 +77,12 @@ static void nvme_addr_read(NvmeCtrl *n, hwaddr addr, void *buf, int size)
static int nvme_check_sqid(NvmeCtrl *n, uint16_t sqid) static int nvme_check_sqid(NvmeCtrl *n, uint16_t sqid)
{ {
return sqid < n->num_queues && n->sq[sqid] != NULL ? 0 : -1; return sqid < n->params.num_queues && n->sq[sqid] != NULL ? 0 : -1;
} }
static int nvme_check_cqid(NvmeCtrl *n, uint16_t cqid) static int nvme_check_cqid(NvmeCtrl *n, uint16_t cqid)
{ {
return cqid < n->num_queues && n->cq[cqid] != NULL ? 0 : -1; return cqid < n->params.num_queues && n->cq[cqid] != NULL ? 0 : -1;
} }
static void nvme_inc_cq_tail(NvmeCQueue *cq) static void nvme_inc_cq_tail(NvmeCQueue *cq)
@ -644,7 +644,7 @@ static uint16_t nvme_create_cq(NvmeCtrl *n, NvmeCmd *cmd)
trace_pci_nvme_err_invalid_create_cq_addr(prp1); trace_pci_nvme_err_invalid_create_cq_addr(prp1);
return NVME_INVALID_FIELD | NVME_DNR; return NVME_INVALID_FIELD | NVME_DNR;
} }
if (unlikely(vector > n->num_queues)) { if (unlikely(vector > n->params.num_queues)) {
trace_pci_nvme_err_invalid_create_cq_vector(vector); trace_pci_nvme_err_invalid_create_cq_vector(vector);
return NVME_INVALID_IRQ_VECTOR | NVME_DNR; return NVME_INVALID_IRQ_VECTOR | NVME_DNR;
} }
@ -796,7 +796,8 @@ static uint16_t nvme_get_feature(NvmeCtrl *n, NvmeCmd *cmd, NvmeRequest *req)
trace_pci_nvme_getfeat_vwcache(result ? "enabled" : "disabled"); trace_pci_nvme_getfeat_vwcache(result ? "enabled" : "disabled");
break; break;
case NVME_NUMBER_OF_QUEUES: case NVME_NUMBER_OF_QUEUES:
result = cpu_to_le32((n->num_queues - 2) | ((n->num_queues - 2) << 16)); result = cpu_to_le32((n->params.num_queues - 2) |
((n->params.num_queues - 2) << 16));
trace_pci_nvme_getfeat_numq(result); trace_pci_nvme_getfeat_numq(result);
break; break;
case NVME_TIMESTAMP: case NVME_TIMESTAMP:
@ -840,9 +841,10 @@ static uint16_t nvme_set_feature(NvmeCtrl *n, NvmeCmd *cmd, NvmeRequest *req)
case NVME_NUMBER_OF_QUEUES: case NVME_NUMBER_OF_QUEUES:
trace_pci_nvme_setfeat_numq((dw11 & 0xFFFF) + 1, trace_pci_nvme_setfeat_numq((dw11 & 0xFFFF) + 1,
((dw11 >> 16) & 0xFFFF) + 1, ((dw11 >> 16) & 0xFFFF) + 1,
n->num_queues - 1, n->num_queues - 1); n->params.num_queues - 1,
req->cqe.result = n->params.num_queues - 1);
cpu_to_le32((n->num_queues - 2) | ((n->num_queues - 2) << 16)); req->cqe.result = cpu_to_le32((n->params.num_queues - 2) |
((n->params.num_queues - 2) << 16));
break; break;
case NVME_TIMESTAMP: case NVME_TIMESTAMP:
return nvme_set_feature_timestamp(n, cmd); return nvme_set_feature_timestamp(n, cmd);
@ -913,12 +915,12 @@ static void nvme_clear_ctrl(NvmeCtrl *n)
blk_drain(n->conf.blk); blk_drain(n->conf.blk);
for (i = 0; i < n->num_queues; i++) { for (i = 0; i < n->params.num_queues; i++) {
if (n->sq[i] != NULL) { if (n->sq[i] != NULL) {
nvme_free_sq(n->sq[i], n); nvme_free_sq(n->sq[i], n);
} }
} }
for (i = 0; i < n->num_queues; i++) { for (i = 0; i < n->params.num_queues; i++) {
if (n->cq[i] != NULL) { if (n->cq[i] != NULL) {
nvme_free_cq(n->cq[i], n); nvme_free_cq(n->cq[i], n);
} }
@ -1348,7 +1350,7 @@ static void nvme_realize(PCIDevice *pci_dev, Error **errp)
int64_t bs_size; int64_t bs_size;
uint8_t *pci_conf; uint8_t *pci_conf;
if (!n->num_queues) { if (!n->params.num_queues) {
error_setg(errp, "num_queues can't be zero"); error_setg(errp, "num_queues can't be zero");
return; return;
} }
@ -1364,12 +1366,12 @@ static void nvme_realize(PCIDevice *pci_dev, Error **errp)
return; return;
} }
if (!n->serial) { if (!n->params.serial) {
error_setg(errp, "serial property not set"); error_setg(errp, "serial property not set");
return; return;
} }
if (!n->cmb_size_mb && n->pmrdev) { if (!n->params.cmb_size_mb && n->pmrdev) {
if (host_memory_backend_is_mapped(n->pmrdev)) { if (host_memory_backend_is_mapped(n->pmrdev)) {
char *path = object_get_canonical_path_component(OBJECT(n->pmrdev)); char *path = object_get_canonical_path_component(OBJECT(n->pmrdev));
error_setg(errp, "can't use already busy memdev: %s", path); error_setg(errp, "can't use already busy memdev: %s", path);
@ -1400,25 +1402,26 @@ static void nvme_realize(PCIDevice *pci_dev, Error **errp)
n->num_namespaces = 1; n->num_namespaces = 1;
/* num_queues is really number of pairs, so each has two doorbells */ /* num_queues is really number of pairs, so each has two doorbells */
n->reg_size = pow2ceil(NVME_REG_SIZE + 2 * n->num_queues * NVME_DB_SIZE); n->reg_size = pow2ceil(NVME_REG_SIZE +
2 * n->params.num_queues * NVME_DB_SIZE);
n->ns_size = bs_size / (uint64_t)n->num_namespaces; n->ns_size = bs_size / (uint64_t)n->num_namespaces;
n->namespaces = g_new0(NvmeNamespace, n->num_namespaces); n->namespaces = g_new0(NvmeNamespace, n->num_namespaces);
n->sq = g_new0(NvmeSQueue *, n->num_queues); n->sq = g_new0(NvmeSQueue *, n->params.num_queues);
n->cq = g_new0(NvmeCQueue *, n->num_queues); n->cq = g_new0(NvmeCQueue *, n->params.num_queues);
memory_region_init_io(&n->iomem, OBJECT(n), &nvme_mmio_ops, n, memory_region_init_io(&n->iomem, OBJECT(n), &nvme_mmio_ops, n,
"nvme", n->reg_size); "nvme", n->reg_size);
pci_register_bar(pci_dev, 0, pci_register_bar(pci_dev, 0,
PCI_BASE_ADDRESS_SPACE_MEMORY | PCI_BASE_ADDRESS_MEM_TYPE_64, PCI_BASE_ADDRESS_SPACE_MEMORY | PCI_BASE_ADDRESS_MEM_TYPE_64,
&n->iomem); &n->iomem);
msix_init_exclusive_bar(pci_dev, n->num_queues, 4, NULL); msix_init_exclusive_bar(pci_dev, n->params.num_queues, 4, NULL);
id->vid = cpu_to_le16(pci_get_word(pci_conf + PCI_VENDOR_ID)); id->vid = cpu_to_le16(pci_get_word(pci_conf + PCI_VENDOR_ID));
id->ssvid = cpu_to_le16(pci_get_word(pci_conf + PCI_SUBSYSTEM_VENDOR_ID)); id->ssvid = cpu_to_le16(pci_get_word(pci_conf + PCI_SUBSYSTEM_VENDOR_ID));
strpadcpy((char *)id->mn, sizeof(id->mn), "QEMU NVMe Ctrl", ' '); strpadcpy((char *)id->mn, sizeof(id->mn), "QEMU NVMe Ctrl", ' ');
strpadcpy((char *)id->fr, sizeof(id->fr), "1.0", ' '); strpadcpy((char *)id->fr, sizeof(id->fr), "1.0", ' ');
strpadcpy((char *)id->sn, sizeof(id->sn), n->serial, ' '); strpadcpy((char *)id->sn, sizeof(id->sn), n->params.serial, ' ');
id->rab = 6; id->rab = 6;
id->ieee[0] = 0x00; id->ieee[0] = 0x00;
id->ieee[1] = 0x02; id->ieee[1] = 0x02;
@ -1447,7 +1450,7 @@ static void nvme_realize(PCIDevice *pci_dev, Error **errp)
n->bar.vs = 0x00010200; n->bar.vs = 0x00010200;
n->bar.intmc = n->bar.intms = 0; n->bar.intmc = n->bar.intms = 0;
if (n->cmb_size_mb) { if (n->params.cmb_size_mb) {
NVME_CMBLOC_SET_BIR(n->bar.cmbloc, 2); NVME_CMBLOC_SET_BIR(n->bar.cmbloc, 2);
NVME_CMBLOC_SET_OFST(n->bar.cmbloc, 0); NVME_CMBLOC_SET_OFST(n->bar.cmbloc, 0);
@ -1458,7 +1461,7 @@ static void nvme_realize(PCIDevice *pci_dev, Error **errp)
NVME_CMBSZ_SET_RDS(n->bar.cmbsz, 1); NVME_CMBSZ_SET_RDS(n->bar.cmbsz, 1);
NVME_CMBSZ_SET_WDS(n->bar.cmbsz, 1); NVME_CMBSZ_SET_WDS(n->bar.cmbsz, 1);
NVME_CMBSZ_SET_SZU(n->bar.cmbsz, 2); /* MBs */ NVME_CMBSZ_SET_SZU(n->bar.cmbsz, 2); /* MBs */
NVME_CMBSZ_SET_SZ(n->bar.cmbsz, n->cmb_size_mb); NVME_CMBSZ_SET_SZ(n->bar.cmbsz, n->params.cmb_size_mb);
n->cmbloc = n->bar.cmbloc; n->cmbloc = n->bar.cmbloc;
n->cmbsz = n->bar.cmbsz; n->cmbsz = n->bar.cmbsz;
@ -1542,7 +1545,7 @@ static void nvme_exit(PCIDevice *pci_dev)
g_free(n->cq); g_free(n->cq);
g_free(n->sq); g_free(n->sq);
if (n->cmb_size_mb) { if (n->params.cmb_size_mb) {
g_free(n->cmbuf); g_free(n->cmbuf);
} }
@ -1556,9 +1559,9 @@ static Property nvme_props[] = {
DEFINE_BLOCK_PROPERTIES(NvmeCtrl, conf), DEFINE_BLOCK_PROPERTIES(NvmeCtrl, conf),
DEFINE_PROP_LINK("pmrdev", NvmeCtrl, pmrdev, TYPE_MEMORY_BACKEND, DEFINE_PROP_LINK("pmrdev", NvmeCtrl, pmrdev, TYPE_MEMORY_BACKEND,
HostMemoryBackend *), HostMemoryBackend *),
DEFINE_PROP_STRING("serial", NvmeCtrl, serial), DEFINE_PROP_STRING("serial", NvmeCtrl, params.serial),
DEFINE_PROP_UINT32("cmb_size_mb", NvmeCtrl, cmb_size_mb, 0), DEFINE_PROP_UINT32("cmb_size_mb", NvmeCtrl, params.cmb_size_mb, 0),
DEFINE_PROP_UINT32("num_queues", NvmeCtrl, num_queues, 64), DEFINE_PROP_UINT32("num_queues", NvmeCtrl, params.num_queues, 64),
DEFINE_PROP_END_OF_LIST(), DEFINE_PROP_END_OF_LIST(),
}; };

11
hw/block/nvme.h
View File

@ -1,7 +1,14 @@
#ifndef HW_NVME_H #ifndef HW_NVME_H
#define HW_NVME_H #define HW_NVME_H
#include "block/nvme.h" #include "block/nvme.h"
typedef struct NvmeParams {
char *serial;
uint32_t num_queues;
uint32_t cmb_size_mb;
} NvmeParams;
typedef struct NvmeAsyncEvent { typedef struct NvmeAsyncEvent {
QSIMPLEQ_ENTRY(NvmeAsyncEvent) entry; QSIMPLEQ_ENTRY(NvmeAsyncEvent) entry;
NvmeAerResult result; NvmeAerResult result;
@ -63,6 +70,7 @@ typedef struct NvmeCtrl {
MemoryRegion ctrl_mem; MemoryRegion ctrl_mem;
NvmeBar bar; NvmeBar bar;
BlockConf conf; BlockConf conf;
NvmeParams params;
uint32_t page_size; uint32_t page_size;
uint16_t page_bits; uint16_t page_bits;
@ -71,10 +79,8 @@ typedef struct NvmeCtrl {
uint16_t sqe_size; uint16_t sqe_size;
uint32_t reg_size; uint32_t reg_size;
uint32_t num_namespaces; uint32_t num_namespaces;
uint32_t num_queues;
uint32_t max_q_ents; uint32_t max_q_ents;
uint64_t ns_size; uint64_t ns_size;
uint32_t cmb_size_mb;
uint32_t cmbsz; uint32_t cmbsz;
uint32_t cmbloc; uint32_t cmbloc;
uint8_t *cmbuf; uint8_t *cmbuf;
@ -82,7 +88,6 @@ typedef struct NvmeCtrl {
uint64_t host_timestamp; /* Timestamp sent by the host */ uint64_t host_timestamp; /* Timestamp sent by the host */
uint64_t timestamp_set_qemu_clock_ms; /* QEMU clock time */ uint64_t timestamp_set_qemu_clock_ms; /* QEMU clock time */
char *serial;
HostMemoryBackend *pmrdev; HostMemoryBackend *pmrdev;
NvmeNamespace *namespaces; NvmeNamespace *namespaces;