target/riscv: Fix checkpatch warning may triggered in csr_ops table
Fix the lines with over 80 characters Fix the lines which are obviously misalgined with other lines in the same group Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn> Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Andrew Jones <ajones@ventanamicro.com> Message-Id: <20220718130955.11899-4-liweiwei@iscas.ac.cn> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
This commit is contained in:
Weiwei Li
Alistair Francis
parent
756b0374dc
commit
108c4f26ce
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@ -3461,20 +3461,20 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
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[CSR_FRM] = { "frm", fs, read_frm, write_frm },
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[CSR_FCSR] = { "fcsr", fs, read_fcsr, write_fcsr },
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/* Vector CSRs */
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[CSR_VSTART] = { "vstart", vs, read_vstart, write_vstart,
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.min_priv_ver = PRIV_VERSION_1_12_0 },
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[CSR_VXSAT] = { "vxsat", vs, read_vxsat, write_vxsat,
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.min_priv_ver = PRIV_VERSION_1_12_0 },
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[CSR_VXRM] = { "vxrm", vs, read_vxrm, write_vxrm,
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.min_priv_ver = PRIV_VERSION_1_12_0 },
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[CSR_VCSR] = { "vcsr", vs, read_vcsr, write_vcsr,
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.min_priv_ver = PRIV_VERSION_1_12_0 },
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[CSR_VL] = { "vl", vs, read_vl,
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.min_priv_ver = PRIV_VERSION_1_12_0 },
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[CSR_VTYPE] = { "vtype", vs, read_vtype,
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.min_priv_ver = PRIV_VERSION_1_12_0 },
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[CSR_VLENB] = { "vlenb", vs, read_vlenb,
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.min_priv_ver = PRIV_VERSION_1_12_0 },
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[CSR_VSTART] = { "vstart", vs, read_vstart, write_vstart,
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.min_priv_ver = PRIV_VERSION_1_12_0 },
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[CSR_VXSAT] = { "vxsat", vs, read_vxsat, write_vxsat,
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.min_priv_ver = PRIV_VERSION_1_12_0 },
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[CSR_VXRM] = { "vxrm", vs, read_vxrm, write_vxrm,
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.min_priv_ver = PRIV_VERSION_1_12_0 },
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[CSR_VCSR] = { "vcsr", vs, read_vcsr, write_vcsr,
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.min_priv_ver = PRIV_VERSION_1_12_0 },
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[CSR_VL] = { "vl", vs, read_vl,
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.min_priv_ver = PRIV_VERSION_1_12_0 },
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[CSR_VTYPE] = { "vtype", vs, read_vtype,
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.min_priv_ver = PRIV_VERSION_1_12_0 },
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[CSR_VLENB] = { "vlenb", vs, read_vlenb,
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.min_priv_ver = PRIV_VERSION_1_12_0 },
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/* User Timers and Counters */
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[CSR_CYCLE] = { "cycle", ctr, read_hpmcounter },
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[CSR_INSTRET] = { "instret", ctr, read_hpmcounter },
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@ -3493,10 +3493,14 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
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#if !defined(CONFIG_USER_ONLY)
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/* Machine Timers and Counters */
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[CSR_MCYCLE] = { "mcycle", any, read_hpmcounter, write_mhpmcounter},
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[CSR_MINSTRET] = { "minstret", any, read_hpmcounter, write_mhpmcounter},
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[CSR_MCYCLEH] = { "mcycleh", any32, read_hpmcounterh, write_mhpmcounterh},
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[CSR_MINSTRETH] = { "minstreth", any32, read_hpmcounterh, write_mhpmcounterh},
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[CSR_MCYCLE] = { "mcycle", any, read_hpmcounter,
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write_mhpmcounter },
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[CSR_MINSTRET] = { "minstret", any, read_hpmcounter,
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write_mhpmcounter },
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[CSR_MCYCLEH] = { "mcycleh", any32, read_hpmcounterh,
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write_mhpmcounterh },
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[CSR_MINSTRETH] = { "minstreth", any32, read_hpmcounterh,
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write_mhpmcounterh },
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/* Machine Information Registers */
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[CSR_MVENDORID] = { "mvendorid", any, read_mvendorid },
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@ -3505,23 +3509,25 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
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[CSR_MHARTID] = { "mhartid", any, read_mhartid },
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[CSR_MCONFIGPTR] = { "mconfigptr", any, read_zero,
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.min_priv_ver = PRIV_VERSION_1_12_0 },
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.min_priv_ver = PRIV_VERSION_1_12_0 },
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/* Machine Trap Setup */
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[CSR_MSTATUS] = { "mstatus", any, read_mstatus, write_mstatus, NULL,
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read_mstatus_i128 },
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[CSR_MISA] = { "misa", any, read_misa, write_misa, NULL,
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read_misa_i128 },
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[CSR_MIDELEG] = { "mideleg", any, NULL, NULL, rmw_mideleg },
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[CSR_MEDELEG] = { "medeleg", any, read_medeleg, write_medeleg },
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[CSR_MIE] = { "mie", any, NULL, NULL, rmw_mie },
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[CSR_MTVEC] = { "mtvec", any, read_mtvec, write_mtvec },
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[CSR_MCOUNTEREN] = { "mcounteren", any, read_mcounteren, write_mcounteren },
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[CSR_MSTATUS] = { "mstatus", any, read_mstatus, write_mstatus,
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NULL, read_mstatus_i128 },
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[CSR_MISA] = { "misa", any, read_misa, write_misa,
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NULL, read_misa_i128 },
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[CSR_MIDELEG] = { "mideleg", any, NULL, NULL, rmw_mideleg },
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[CSR_MEDELEG] = { "medeleg", any, read_medeleg, write_medeleg },
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[CSR_MIE] = { "mie", any, NULL, NULL, rmw_mie },
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[CSR_MTVEC] = { "mtvec", any, read_mtvec, write_mtvec },
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[CSR_MCOUNTEREN] = { "mcounteren", any, read_mcounteren,
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write_mcounteren },
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[CSR_MSTATUSH] = { "mstatush", any32, read_mstatush, write_mstatush },
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[CSR_MSTATUSH] = { "mstatush", any32, read_mstatush,
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write_mstatush },
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/* Machine Trap Handling */
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[CSR_MSCRATCH] = { "mscratch", any, read_mscratch, write_mscratch, NULL,
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read_mscratch_i128, write_mscratch_i128 },
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[CSR_MSCRATCH] = { "mscratch", any, read_mscratch, write_mscratch,
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NULL, read_mscratch_i128, write_mscratch_i128 },
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[CSR_MEPC] = { "mepc", any, read_mepc, write_mepc },
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[CSR_MCAUSE] = { "mcause", any, read_mcause, write_mcause },
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[CSR_MTVAL] = { "mtval", any, read_mtval, write_mtval },
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@ -3532,12 +3538,12 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
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[CSR_MIREG] = { "mireg", aia_any, NULL, NULL, rmw_xireg },
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/* Machine-Level Interrupts (AIA) */
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[CSR_MTOPEI] = { "mtopei", aia_any, NULL, NULL, rmw_xtopei },
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[CSR_MTOPI] = { "mtopi", aia_any, read_mtopi },
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[CSR_MTOPEI] = { "mtopei", aia_any, NULL, NULL, rmw_xtopei },
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[CSR_MTOPI] = { "mtopi", aia_any, read_mtopi },
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/* Virtual Interrupts for Supervisor Level (AIA) */
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[CSR_MVIEN] = { "mvien", aia_any, read_zero, write_ignore },
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[CSR_MVIP] = { "mvip", aia_any, read_zero, write_ignore },
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[CSR_MVIEN] = { "mvien", aia_any, read_zero, write_ignore },
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[CSR_MVIP] = { "mvip", aia_any, read_zero, write_ignore },
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/* Machine-Level High-Half CSRs (AIA) */
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[CSR_MIDELEGH] = { "midelegh", aia_any32, NULL, NULL, rmw_midelegh },
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@ -3548,33 +3554,34 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
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/* Execution environment configuration */
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[CSR_MENVCFG] = { "menvcfg", any, read_menvcfg, write_menvcfg,
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.min_priv_ver = PRIV_VERSION_1_12_0 },
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.min_priv_ver = PRIV_VERSION_1_12_0 },
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[CSR_MENVCFGH] = { "menvcfgh", any32, read_menvcfgh, write_menvcfgh,
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.min_priv_ver = PRIV_VERSION_1_12_0 },
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.min_priv_ver = PRIV_VERSION_1_12_0 },
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[CSR_SENVCFG] = { "senvcfg", smode, read_senvcfg, write_senvcfg,
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.min_priv_ver = PRIV_VERSION_1_12_0 },
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.min_priv_ver = PRIV_VERSION_1_12_0 },
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[CSR_HENVCFG] = { "henvcfg", hmode, read_henvcfg, write_henvcfg,
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.min_priv_ver = PRIV_VERSION_1_12_0 },
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.min_priv_ver = PRIV_VERSION_1_12_0 },
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[CSR_HENVCFGH] = { "henvcfgh", hmode32, read_henvcfgh, write_henvcfgh,
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.min_priv_ver = PRIV_VERSION_1_12_0 },
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.min_priv_ver = PRIV_VERSION_1_12_0 },
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/* Supervisor Trap Setup */
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[CSR_SSTATUS] = { "sstatus", smode, read_sstatus, write_sstatus, NULL,
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read_sstatus_i128 },
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[CSR_SIE] = { "sie", smode, NULL, NULL, rmw_sie },
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[CSR_STVEC] = { "stvec", smode, read_stvec, write_stvec },
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[CSR_SCOUNTEREN] = { "scounteren", smode, read_scounteren, write_scounteren },
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[CSR_SSTATUS] = { "sstatus", smode, read_sstatus, write_sstatus,
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NULL, read_sstatus_i128 },
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[CSR_SIE] = { "sie", smode, NULL, NULL, rmw_sie },
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[CSR_STVEC] = { "stvec", smode, read_stvec, write_stvec },
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[CSR_SCOUNTEREN] = { "scounteren", smode, read_scounteren,
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write_scounteren },
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/* Supervisor Trap Handling */
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[CSR_SSCRATCH] = { "sscratch", smode, read_sscratch, write_sscratch, NULL,
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read_sscratch_i128, write_sscratch_i128 },
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[CSR_SSCRATCH] = { "sscratch", smode, read_sscratch, write_sscratch,
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NULL, read_sscratch_i128, write_sscratch_i128 },
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[CSR_SEPC] = { "sepc", smode, read_sepc, write_sepc },
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[CSR_SCAUSE] = { "scause", smode, read_scause, write_scause },
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[CSR_STVAL] = { "stval", smode, read_stval, write_stval },
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[CSR_STVAL] = { "stval", smode, read_stval, write_stval },
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[CSR_SIP] = { "sip", smode, NULL, NULL, rmw_sip },
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/* Supervisor Protection and Translation */
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[CSR_SATP] = { "satp", smode, read_satp, write_satp },
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[CSR_SATP] = { "satp", smode, read_satp, write_satp },
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/* Supervisor-Level Window to Indirectly Accessed Registers (AIA) */
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[CSR_SISELECT] = { "siselect", aia_smode, NULL, NULL, rmw_xiselect },
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@ -3588,87 +3595,100 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
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[CSR_SIEH] = { "sieh", aia_smode32, NULL, NULL, rmw_sieh },
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[CSR_SIPH] = { "siph", aia_smode32, NULL, NULL, rmw_siph },
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[CSR_HSTATUS] = { "hstatus", hmode, read_hstatus, write_hstatus,
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.min_priv_ver = PRIV_VERSION_1_12_0 },
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[CSR_HEDELEG] = { "hedeleg", hmode, read_hedeleg, write_hedeleg,
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.min_priv_ver = PRIV_VERSION_1_12_0 },
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[CSR_HSTATUS] = { "hstatus", hmode, read_hstatus, write_hstatus,
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.min_priv_ver = PRIV_VERSION_1_12_0 },
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[CSR_HEDELEG] = { "hedeleg", hmode, read_hedeleg, write_hedeleg,
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.min_priv_ver = PRIV_VERSION_1_12_0 },
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[CSR_HIDELEG] = { "hideleg", hmode, NULL, NULL, rmw_hideleg,
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.min_priv_ver = PRIV_VERSION_1_12_0 },
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[CSR_HVIP] = { "hvip", hmode, NULL, NULL, rmw_hvip,
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.min_priv_ver = PRIV_VERSION_1_12_0 },
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[CSR_HIP] = { "hip", hmode, NULL, NULL, rmw_hip,
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.min_priv_ver = PRIV_VERSION_1_12_0 },
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[CSR_HIE] = { "hie", hmode, NULL, NULL, rmw_hie,
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.min_priv_ver = PRIV_VERSION_1_12_0 },
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[CSR_HCOUNTEREN] = { "hcounteren", hmode, read_hcounteren, write_hcounteren,
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.min_priv_ver = PRIV_VERSION_1_12_0 },
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[CSR_HGEIE] = { "hgeie", hmode, read_hgeie, write_hgeie,
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.min_priv_ver = PRIV_VERSION_1_12_0 },
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[CSR_HTVAL] = { "htval", hmode, read_htval, write_htval,
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.min_priv_ver = PRIV_VERSION_1_12_0 },
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[CSR_HTINST] = { "htinst", hmode, read_htinst, write_htinst,
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.min_priv_ver = PRIV_VERSION_1_12_0 },
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.min_priv_ver = PRIV_VERSION_1_12_0 },
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[CSR_HVIP] = { "hvip", hmode, NULL, NULL, rmw_hvip,
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.min_priv_ver = PRIV_VERSION_1_12_0 },
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[CSR_HIP] = { "hip", hmode, NULL, NULL, rmw_hip,
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.min_priv_ver = PRIV_VERSION_1_12_0 },
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[CSR_HIE] = { "hie", hmode, NULL, NULL, rmw_hie,
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.min_priv_ver = PRIV_VERSION_1_12_0 },
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[CSR_HCOUNTEREN] = { "hcounteren", hmode, read_hcounteren,
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write_hcounteren,
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.min_priv_ver = PRIV_VERSION_1_12_0 },
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[CSR_HGEIE] = { "hgeie", hmode, read_hgeie, write_hgeie,
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.min_priv_ver = PRIV_VERSION_1_12_0 },
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[CSR_HTVAL] = { "htval", hmode, read_htval, write_htval,
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.min_priv_ver = PRIV_VERSION_1_12_0 },
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[CSR_HTINST] = { "htinst", hmode, read_htinst, write_htinst,
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.min_priv_ver = PRIV_VERSION_1_12_0 },
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[CSR_HGEIP] = { "hgeip", hmode, read_hgeip,
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.min_priv_ver = PRIV_VERSION_1_12_0 },
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[CSR_HGATP] = { "hgatp", hmode, read_hgatp, write_hgatp,
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.min_priv_ver = PRIV_VERSION_1_12_0 },
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[CSR_HTIMEDELTA] = { "htimedelta", hmode, read_htimedelta, write_htimedelta,
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.min_priv_ver = PRIV_VERSION_1_12_0 },
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[CSR_HTIMEDELTAH] = { "htimedeltah", hmode32, read_htimedeltah, write_htimedeltah,
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.min_priv_ver = PRIV_VERSION_1_12_0 },
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.min_priv_ver = PRIV_VERSION_1_12_0 },
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[CSR_HGATP] = { "hgatp", hmode, read_hgatp, write_hgatp,
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.min_priv_ver = PRIV_VERSION_1_12_0 },
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[CSR_HTIMEDELTA] = { "htimedelta", hmode, read_htimedelta,
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write_htimedelta,
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.min_priv_ver = PRIV_VERSION_1_12_0 },
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[CSR_HTIMEDELTAH] = { "htimedeltah", hmode32, read_htimedeltah,
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write_htimedeltah,
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.min_priv_ver = PRIV_VERSION_1_12_0 },
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[CSR_VSSTATUS] = { "vsstatus", hmode, read_vsstatus, write_vsstatus,
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.min_priv_ver = PRIV_VERSION_1_12_0 },
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[CSR_VSIP] = { "vsip", hmode, NULL, NULL, rmw_vsip,
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.min_priv_ver = PRIV_VERSION_1_12_0 },
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[CSR_VSIE] = { "vsie", hmode, NULL, NULL, rmw_vsie ,
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.min_priv_ver = PRIV_VERSION_1_12_0 },
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[CSR_VSTVEC] = { "vstvec", hmode, read_vstvec, write_vstvec,
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.min_priv_ver = PRIV_VERSION_1_12_0 },
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[CSR_VSSCRATCH] = { "vsscratch", hmode, read_vsscratch, write_vsscratch,
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.min_priv_ver = PRIV_VERSION_1_12_0 },
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[CSR_VSEPC] = { "vsepc", hmode, read_vsepc, write_vsepc,
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.min_priv_ver = PRIV_VERSION_1_12_0 },
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[CSR_VSCAUSE] = { "vscause", hmode, read_vscause, write_vscause,
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.min_priv_ver = PRIV_VERSION_1_12_0 },
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[CSR_VSTVAL] = { "vstval", hmode, read_vstval, write_vstval,
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.min_priv_ver = PRIV_VERSION_1_12_0 },
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[CSR_VSATP] = { "vsatp", hmode, read_vsatp, write_vsatp,
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.min_priv_ver = PRIV_VERSION_1_12_0 },
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[CSR_VSSTATUS] = { "vsstatus", hmode, read_vsstatus,
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write_vsstatus,
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.min_priv_ver = PRIV_VERSION_1_12_0 },
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[CSR_VSIP] = { "vsip", hmode, NULL, NULL, rmw_vsip,
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.min_priv_ver = PRIV_VERSION_1_12_0 },
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[CSR_VSIE] = { "vsie", hmode, NULL, NULL, rmw_vsie ,
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.min_priv_ver = PRIV_VERSION_1_12_0 },
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[CSR_VSTVEC] = { "vstvec", hmode, read_vstvec, write_vstvec,
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.min_priv_ver = PRIV_VERSION_1_12_0 },
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[CSR_VSSCRATCH] = { "vsscratch", hmode, read_vsscratch,
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write_vsscratch,
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.min_priv_ver = PRIV_VERSION_1_12_0 },
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[CSR_VSEPC] = { "vsepc", hmode, read_vsepc, write_vsepc,
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.min_priv_ver = PRIV_VERSION_1_12_0 },
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[CSR_VSCAUSE] = { "vscause", hmode, read_vscause, write_vscause,
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.min_priv_ver = PRIV_VERSION_1_12_0 },
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[CSR_VSTVAL] = { "vstval", hmode, read_vstval, write_vstval,
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.min_priv_ver = PRIV_VERSION_1_12_0 },
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[CSR_VSATP] = { "vsatp", hmode, read_vsatp, write_vsatp,
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.min_priv_ver = PRIV_VERSION_1_12_0 },
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[CSR_MTVAL2] = { "mtval2", hmode, read_mtval2, write_mtval2,
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.min_priv_ver = PRIV_VERSION_1_12_0 },
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[CSR_MTINST] = { "mtinst", hmode, read_mtinst, write_mtinst,
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.min_priv_ver = PRIV_VERSION_1_12_0 },
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[CSR_MTVAL2] = { "mtval2", hmode, read_mtval2, write_mtval2,
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.min_priv_ver = PRIV_VERSION_1_12_0 },
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[CSR_MTINST] = { "mtinst", hmode, read_mtinst, write_mtinst,
|
||||
.min_priv_ver = PRIV_VERSION_1_12_0 },
|
||||
|
||||
/* Virtual Interrupts and Interrupt Priorities (H-extension with AIA) */
|
||||
[CSR_HVIEN] = { "hvien", aia_hmode, read_zero, write_ignore },
|
||||
[CSR_HVICTL] = { "hvictl", aia_hmode, read_hvictl, write_hvictl },
|
||||
[CSR_HVIPRIO1] = { "hviprio1", aia_hmode, read_hviprio1, write_hviprio1 },
|
||||
[CSR_HVIPRIO2] = { "hviprio2", aia_hmode, read_hviprio2, write_hviprio2 },
|
||||
[CSR_HVICTL] = { "hvictl", aia_hmode, read_hvictl,
|
||||
write_hvictl },
|
||||
[CSR_HVIPRIO1] = { "hviprio1", aia_hmode, read_hviprio1,
|
||||
write_hviprio1 },
|
||||
[CSR_HVIPRIO2] = { "hviprio2", aia_hmode, read_hviprio2,
|
||||
write_hviprio2 },
|
||||
|
||||
/*
|
||||
* VS-Level Window to Indirectly Accessed Registers (H-extension with AIA)
|
||||
*/
|
||||
[CSR_VSISELECT] = { "vsiselect", aia_hmode, NULL, NULL, rmw_xiselect },
|
||||
[CSR_VSIREG] = { "vsireg", aia_hmode, NULL, NULL, rmw_xireg },
|
||||
[CSR_VSISELECT] = { "vsiselect", aia_hmode, NULL, NULL,
|
||||
rmw_xiselect },
|
||||
[CSR_VSIREG] = { "vsireg", aia_hmode, NULL, NULL, rmw_xireg },
|
||||
|
||||
/* VS-Level Interrupts (H-extension with AIA) */
|
||||
[CSR_VSTOPEI] = { "vstopei", aia_hmode, NULL, NULL, rmw_xtopei },
|
||||
[CSR_VSTOPI] = { "vstopi", aia_hmode, read_vstopi },
|
||||
|
||||
/* Hypervisor and VS-Level High-Half CSRs (H-extension with AIA) */
|
||||
[CSR_HIDELEGH] = { "hidelegh", aia_hmode32, NULL, NULL, rmw_hidelegh },
|
||||
[CSR_HVIENH] = { "hvienh", aia_hmode32, read_zero, write_ignore },
|
||||
[CSR_HIDELEGH] = { "hidelegh", aia_hmode32, NULL, NULL,
|
||||
rmw_hidelegh },
|
||||
[CSR_HVIENH] = { "hvienh", aia_hmode32, read_zero,
|
||||
write_ignore },
|
||||
[CSR_HVIPH] = { "hviph", aia_hmode32, NULL, NULL, rmw_hviph },
|
||||
[CSR_HVIPRIO1H] = { "hviprio1h", aia_hmode32, read_hviprio1h, write_hviprio1h },
|
||||
[CSR_HVIPRIO2H] = { "hviprio2h", aia_hmode32, read_hviprio2h, write_hviprio2h },
|
||||
[CSR_HVIPRIO1H] = { "hviprio1h", aia_hmode32, read_hviprio1h,
|
||||
write_hviprio1h },
|
||||
[CSR_HVIPRIO2H] = { "hviprio2h", aia_hmode32, read_hviprio2h,
|
||||
write_hviprio2h },
|
||||
[CSR_VSIEH] = { "vsieh", aia_hmode32, NULL, NULL, rmw_vsieh },
|
||||
[CSR_VSIPH] = { "vsiph", aia_hmode32, NULL, NULL, rmw_vsiph },
|
||||
|
||||
/* Physical Memory Protection */
|
||||
[CSR_MSECCFG] = { "mseccfg", epmp, read_mseccfg, write_mseccfg,
|
||||
.min_priv_ver = PRIV_VERSION_1_11_0 },
|
||||
.min_priv_ver = PRIV_VERSION_1_11_0 },
|
||||
[CSR_PMPCFG0] = { "pmpcfg0", pmp, read_pmpcfg, write_pmpcfg },
|
||||
[CSR_PMPCFG1] = { "pmpcfg1", pmp, read_pmpcfg, write_pmpcfg },
|
||||
[CSR_PMPCFG2] = { "pmpcfg2", pmp, read_pmpcfg, write_pmpcfg },
|
||||
|
|
@ -3697,17 +3717,23 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
|
|||
[CSR_TDATA3] = { "tdata3", debug, read_tdata, write_tdata },
|
||||
|
||||
/* User Pointer Masking */
|
||||
[CSR_UMTE] = { "umte", pointer_masking, read_umte, write_umte },
|
||||
[CSR_UPMMASK] = { "upmmask", pointer_masking, read_upmmask, write_upmmask },
|
||||
[CSR_UPMBASE] = { "upmbase", pointer_masking, read_upmbase, write_upmbase },
|
||||
[CSR_UMTE] = { "umte", pointer_masking, read_umte, write_umte },
|
||||
[CSR_UPMMASK] = { "upmmask", pointer_masking, read_upmmask,
|
||||
write_upmmask },
|
||||
[CSR_UPMBASE] = { "upmbase", pointer_masking, read_upmbase,
|
||||
write_upmbase },
|
||||
/* Machine Pointer Masking */
|
||||
[CSR_MMTE] = { "mmte", pointer_masking, read_mmte, write_mmte },
|
||||
[CSR_MPMMASK] = { "mpmmask", pointer_masking, read_mpmmask, write_mpmmask },
|
||||
[CSR_MPMBASE] = { "mpmbase", pointer_masking, read_mpmbase, write_mpmbase },
|
||||
[CSR_MMTE] = { "mmte", pointer_masking, read_mmte, write_mmte },
|
||||
[CSR_MPMMASK] = { "mpmmask", pointer_masking, read_mpmmask,
|
||||
write_mpmmask },
|
||||
[CSR_MPMBASE] = { "mpmbase", pointer_masking, read_mpmbase,
|
||||
write_mpmbase },
|
||||
/* Supervisor Pointer Masking */
|
||||
[CSR_SMTE] = { "smte", pointer_masking, read_smte, write_smte },
|
||||
[CSR_SPMMASK] = { "spmmask", pointer_masking, read_spmmask, write_spmmask },
|
||||
[CSR_SPMBASE] = { "spmbase", pointer_masking, read_spmbase, write_spmbase },
|
||||
[CSR_SMTE] = { "smte", pointer_masking, read_smte, write_smte },
|
||||
[CSR_SPMMASK] = { "spmmask", pointer_masking, read_spmmask,
|
||||
write_spmmask },
|
||||
[CSR_SPMBASE] = { "spmbase", pointer_masking, read_spmbase,
|
||||
write_spmbase },
|
||||
|
||||
/* Performance Counters */
|
||||
[CSR_HPMCOUNTER3] = { "hpmcounter3", ctr, read_hpmcounter },
|
||||
|
|
@ -3741,125 +3767,126 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
|
|||
[CSR_HPMCOUNTER31] = { "hpmcounter31", ctr, read_hpmcounter },
|
||||
|
||||
[CSR_MHPMCOUNTER3] = { "mhpmcounter3", mctr, read_hpmcounter,
|
||||
write_mhpmcounter },
|
||||
write_mhpmcounter },
|
||||
[CSR_MHPMCOUNTER4] = { "mhpmcounter4", mctr, read_hpmcounter,
|
||||
write_mhpmcounter },
|
||||
write_mhpmcounter },
|
||||
[CSR_MHPMCOUNTER5] = { "mhpmcounter5", mctr, read_hpmcounter,
|
||||
write_mhpmcounter },
|
||||
write_mhpmcounter },
|
||||
[CSR_MHPMCOUNTER6] = { "mhpmcounter6", mctr, read_hpmcounter,
|
||||
write_mhpmcounter },
|
||||
write_mhpmcounter },
|
||||
[CSR_MHPMCOUNTER7] = { "mhpmcounter7", mctr, read_hpmcounter,
|
||||
write_mhpmcounter },
|
||||
write_mhpmcounter },
|
||||
[CSR_MHPMCOUNTER8] = { "mhpmcounter8", mctr, read_hpmcounter,
|
||||
write_mhpmcounter },
|
||||
write_mhpmcounter },
|
||||
[CSR_MHPMCOUNTER9] = { "mhpmcounter9", mctr, read_hpmcounter,
|
||||
write_mhpmcounter },
|
||||
write_mhpmcounter },
|
||||
[CSR_MHPMCOUNTER10] = { "mhpmcounter10", mctr, read_hpmcounter,
|
||||
write_mhpmcounter },
|
||||
write_mhpmcounter },
|
||||
[CSR_MHPMCOUNTER11] = { "mhpmcounter11", mctr, read_hpmcounter,
|
||||
write_mhpmcounter },
|
||||
write_mhpmcounter },
|
||||
[CSR_MHPMCOUNTER12] = { "mhpmcounter12", mctr, read_hpmcounter,
|
||||
write_mhpmcounter },
|
||||
write_mhpmcounter },
|
||||
[CSR_MHPMCOUNTER13] = { "mhpmcounter13", mctr, read_hpmcounter,
|
||||
write_mhpmcounter },
|
||||
write_mhpmcounter },
|
||||
[CSR_MHPMCOUNTER14] = { "mhpmcounter14", mctr, read_hpmcounter,
|
||||
write_mhpmcounter },
|
||||
write_mhpmcounter },
|
||||
[CSR_MHPMCOUNTER15] = { "mhpmcounter15", mctr, read_hpmcounter,
|
||||
write_mhpmcounter },
|
||||
write_mhpmcounter },
|
||||
[CSR_MHPMCOUNTER16] = { "mhpmcounter16", mctr, read_hpmcounter,
|
||||
write_mhpmcounter },
|
||||
write_mhpmcounter },
|
||||
[CSR_MHPMCOUNTER17] = { "mhpmcounter17", mctr, read_hpmcounter,
|
||||
write_mhpmcounter },
|
||||
write_mhpmcounter },
|
||||
[CSR_MHPMCOUNTER18] = { "mhpmcounter18", mctr, read_hpmcounter,
|
||||
write_mhpmcounter },
|
||||
write_mhpmcounter },
|
||||
[CSR_MHPMCOUNTER19] = { "mhpmcounter19", mctr, read_hpmcounter,
|
||||
write_mhpmcounter },
|
||||
write_mhpmcounter },
|
||||
[CSR_MHPMCOUNTER20] = { "mhpmcounter20", mctr, read_hpmcounter,
|
||||
write_mhpmcounter },
|
||||
write_mhpmcounter },
|
||||
[CSR_MHPMCOUNTER21] = { "mhpmcounter21", mctr, read_hpmcounter,
|
||||
write_mhpmcounter },
|
||||
write_mhpmcounter },
|
||||
[CSR_MHPMCOUNTER22] = { "mhpmcounter22", mctr, read_hpmcounter,
|
||||
write_mhpmcounter },
|
||||
write_mhpmcounter },
|
||||
[CSR_MHPMCOUNTER23] = { "mhpmcounter23", mctr, read_hpmcounter,
|
||||
write_mhpmcounter },
|
||||
write_mhpmcounter },
|
||||
[CSR_MHPMCOUNTER24] = { "mhpmcounter24", mctr, read_hpmcounter,
|
||||
write_mhpmcounter },
|
||||
write_mhpmcounter },
|
||||
[CSR_MHPMCOUNTER25] = { "mhpmcounter25", mctr, read_hpmcounter,
|
||||
write_mhpmcounter },
|
||||
write_mhpmcounter },
|
||||
[CSR_MHPMCOUNTER26] = { "mhpmcounter26", mctr, read_hpmcounter,
|
||||
write_mhpmcounter },
|
||||
write_mhpmcounter },
|
||||
[CSR_MHPMCOUNTER27] = { "mhpmcounter27", mctr, read_hpmcounter,
|
||||
write_mhpmcounter },
|
||||
write_mhpmcounter },
|
||||
[CSR_MHPMCOUNTER28] = { "mhpmcounter28", mctr, read_hpmcounter,
|
||||
write_mhpmcounter },
|
||||
write_mhpmcounter },
|
||||
[CSR_MHPMCOUNTER29] = { "mhpmcounter29", mctr, read_hpmcounter,
|
||||
write_mhpmcounter },
|
||||
write_mhpmcounter },
|
||||
[CSR_MHPMCOUNTER30] = { "mhpmcounter30", mctr, read_hpmcounter,
|
||||
write_mhpmcounter },
|
||||
write_mhpmcounter },
|
||||
[CSR_MHPMCOUNTER31] = { "mhpmcounter31", mctr, read_hpmcounter,
|
||||
write_mhpmcounter },
|
||||
write_mhpmcounter },
|
||||
|
||||
[CSR_MCOUNTINHIBIT] = { "mcountinhibit", any, read_mcountinhibit,
|
||||
write_mcountinhibit, .min_priv_ver = PRIV_VERSION_1_11_0 },
|
||||
write_mcountinhibit,
|
||||
.min_priv_ver = PRIV_VERSION_1_11_0 },
|
||||
|
||||
[CSR_MHPMEVENT3] = { "mhpmevent3", any, read_mhpmevent,
|
||||
write_mhpmevent },
|
||||
write_mhpmevent },
|
||||
[CSR_MHPMEVENT4] = { "mhpmevent4", any, read_mhpmevent,
|
||||
write_mhpmevent },
|
||||
write_mhpmevent },
|
||||
[CSR_MHPMEVENT5] = { "mhpmevent5", any, read_mhpmevent,
|
||||
write_mhpmevent },
|
||||
write_mhpmevent },
|
||||
[CSR_MHPMEVENT6] = { "mhpmevent6", any, read_mhpmevent,
|
||||
write_mhpmevent },
|
||||
write_mhpmevent },
|
||||
[CSR_MHPMEVENT7] = { "mhpmevent7", any, read_mhpmevent,
|
||||
write_mhpmevent },
|
||||
write_mhpmevent },
|
||||
[CSR_MHPMEVENT8] = { "mhpmevent8", any, read_mhpmevent,
|
||||
write_mhpmevent },
|
||||
write_mhpmevent },
|
||||
[CSR_MHPMEVENT9] = { "mhpmevent9", any, read_mhpmevent,
|
||||
write_mhpmevent },
|
||||
write_mhpmevent },
|
||||
[CSR_MHPMEVENT10] = { "mhpmevent10", any, read_mhpmevent,
|
||||
write_mhpmevent },
|
||||
write_mhpmevent },
|
||||
[CSR_MHPMEVENT11] = { "mhpmevent11", any, read_mhpmevent,
|
||||
write_mhpmevent },
|
||||
write_mhpmevent },
|
||||
[CSR_MHPMEVENT12] = { "mhpmevent12", any, read_mhpmevent,
|
||||
write_mhpmevent },
|
||||
write_mhpmevent },
|
||||
[CSR_MHPMEVENT13] = { "mhpmevent13", any, read_mhpmevent,
|
||||
write_mhpmevent },
|
||||
write_mhpmevent },
|
||||
[CSR_MHPMEVENT14] = { "mhpmevent14", any, read_mhpmevent,
|
||||
write_mhpmevent },
|
||||
write_mhpmevent },
|
||||
[CSR_MHPMEVENT15] = { "mhpmevent15", any, read_mhpmevent,
|
||||
write_mhpmevent },
|
||||
write_mhpmevent },
|
||||
[CSR_MHPMEVENT16] = { "mhpmevent16", any, read_mhpmevent,
|
||||
write_mhpmevent },
|
||||
write_mhpmevent },
|
||||
[CSR_MHPMEVENT17] = { "mhpmevent17", any, read_mhpmevent,
|
||||
write_mhpmevent },
|
||||
write_mhpmevent },
|
||||
[CSR_MHPMEVENT18] = { "mhpmevent18", any, read_mhpmevent,
|
||||
write_mhpmevent },
|
||||
write_mhpmevent },
|
||||
[CSR_MHPMEVENT19] = { "mhpmevent19", any, read_mhpmevent,
|
||||
write_mhpmevent },
|
||||
write_mhpmevent },
|
||||
[CSR_MHPMEVENT20] = { "mhpmevent20", any, read_mhpmevent,
|
||||
write_mhpmevent },
|
||||
write_mhpmevent },
|
||||
[CSR_MHPMEVENT21] = { "mhpmevent21", any, read_mhpmevent,
|
||||
write_mhpmevent },
|
||||
write_mhpmevent },
|
||||
[CSR_MHPMEVENT22] = { "mhpmevent22", any, read_mhpmevent,
|
||||
write_mhpmevent },
|
||||
write_mhpmevent },
|
||||
[CSR_MHPMEVENT23] = { "mhpmevent23", any, read_mhpmevent,
|
||||
write_mhpmevent },
|
||||
write_mhpmevent },
|
||||
[CSR_MHPMEVENT24] = { "mhpmevent24", any, read_mhpmevent,
|
||||
write_mhpmevent },
|
||||
write_mhpmevent },
|
||||
[CSR_MHPMEVENT25] = { "mhpmevent25", any, read_mhpmevent,
|
||||
write_mhpmevent },
|
||||
write_mhpmevent },
|
||||
[CSR_MHPMEVENT26] = { "mhpmevent26", any, read_mhpmevent,
|
||||
write_mhpmevent },
|
||||
write_mhpmevent },
|
||||
[CSR_MHPMEVENT27] = { "mhpmevent27", any, read_mhpmevent,
|
||||
write_mhpmevent },
|
||||
write_mhpmevent },
|
||||
[CSR_MHPMEVENT28] = { "mhpmevent28", any, read_mhpmevent,
|
||||
write_mhpmevent },
|
||||
write_mhpmevent },
|
||||
[CSR_MHPMEVENT29] = { "mhpmevent29", any, read_mhpmevent,
|
||||
write_mhpmevent },
|
||||
write_mhpmevent },
|
||||
[CSR_MHPMEVENT30] = { "mhpmevent30", any, read_mhpmevent,
|
||||
write_mhpmevent },
|
||||
write_mhpmevent },
|
||||
[CSR_MHPMEVENT31] = { "mhpmevent31", any, read_mhpmevent,
|
||||
write_mhpmevent },
|
||||
write_mhpmevent },
|
||||
|
||||
[CSR_HPMCOUNTER3H] = { "hpmcounter3h", ctr32, read_hpmcounterh },
|
||||
[CSR_HPMCOUNTER4H] = { "hpmcounter4h", ctr32, read_hpmcounterh },
|
||||
|
|
@ -3892,62 +3919,62 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
|
|||
[CSR_HPMCOUNTER31H] = { "hpmcounter31h", ctr32, read_hpmcounterh },
|
||||
|
||||
[CSR_MHPMCOUNTER3H] = { "mhpmcounter3h", mctr32, read_hpmcounterh,
|
||||
write_mhpmcounterh },
|
||||
write_mhpmcounterh },
|
||||
[CSR_MHPMCOUNTER4H] = { "mhpmcounter4h", mctr32, read_hpmcounterh,
|
||||
write_mhpmcounterh },
|
||||
write_mhpmcounterh },
|
||||
[CSR_MHPMCOUNTER5H] = { "mhpmcounter5h", mctr32, read_hpmcounterh,
|
||||
write_mhpmcounterh },
|
||||
write_mhpmcounterh },
|
||||
[CSR_MHPMCOUNTER6H] = { "mhpmcounter6h", mctr32, read_hpmcounterh,
|
||||
write_mhpmcounterh },
|
||||
write_mhpmcounterh },
|
||||
[CSR_MHPMCOUNTER7H] = { "mhpmcounter7h", mctr32, read_hpmcounterh,
|
||||
write_mhpmcounterh },
|
||||
write_mhpmcounterh },
|
||||
[CSR_MHPMCOUNTER8H] = { "mhpmcounter8h", mctr32, read_hpmcounterh,
|
||||
write_mhpmcounterh },
|
||||
write_mhpmcounterh },
|
||||
[CSR_MHPMCOUNTER9H] = { "mhpmcounter9h", mctr32, read_hpmcounterh,
|
||||
write_mhpmcounterh },
|
||||
write_mhpmcounterh },
|
||||
[CSR_MHPMCOUNTER10H] = { "mhpmcounter10h", mctr32, read_hpmcounterh,
|
||||
write_mhpmcounterh },
|
||||
write_mhpmcounterh },
|
||||
[CSR_MHPMCOUNTER11H] = { "mhpmcounter11h", mctr32, read_hpmcounterh,
|
||||
write_mhpmcounterh },
|
||||
write_mhpmcounterh },
|
||||
[CSR_MHPMCOUNTER12H] = { "mhpmcounter12h", mctr32, read_hpmcounterh,
|
||||
write_mhpmcounterh },
|
||||
write_mhpmcounterh },
|
||||
[CSR_MHPMCOUNTER13H] = { "mhpmcounter13h", mctr32, read_hpmcounterh,
|
||||
write_mhpmcounterh },
|
||||
write_mhpmcounterh },
|
||||
[CSR_MHPMCOUNTER14H] = { "mhpmcounter14h", mctr32, read_hpmcounterh,
|
||||
write_mhpmcounterh },
|
||||
write_mhpmcounterh },
|
||||
[CSR_MHPMCOUNTER15H] = { "mhpmcounter15h", mctr32, read_hpmcounterh,
|
||||
write_mhpmcounterh },
|
||||
write_mhpmcounterh },
|
||||
[CSR_MHPMCOUNTER16H] = { "mhpmcounter16h", mctr32, read_hpmcounterh,
|
||||
write_mhpmcounterh },
|
||||
write_mhpmcounterh },
|
||||
[CSR_MHPMCOUNTER17H] = { "mhpmcounter17h", mctr32, read_hpmcounterh,
|
||||
write_mhpmcounterh },
|
||||
write_mhpmcounterh },
|
||||
[CSR_MHPMCOUNTER18H] = { "mhpmcounter18h", mctr32, read_hpmcounterh,
|
||||
write_mhpmcounterh },
|
||||
write_mhpmcounterh },
|
||||
[CSR_MHPMCOUNTER19H] = { "mhpmcounter19h", mctr32, read_hpmcounterh,
|
||||
write_mhpmcounterh },
|
||||
write_mhpmcounterh },
|
||||
[CSR_MHPMCOUNTER20H] = { "mhpmcounter20h", mctr32, read_hpmcounterh,
|
||||
write_mhpmcounterh },
|
||||
write_mhpmcounterh },
|
||||
[CSR_MHPMCOUNTER21H] = { "mhpmcounter21h", mctr32, read_hpmcounterh,
|
||||
write_mhpmcounterh },
|
||||
write_mhpmcounterh },
|
||||
[CSR_MHPMCOUNTER22H] = { "mhpmcounter22h", mctr32, read_hpmcounterh,
|
||||
write_mhpmcounterh },
|
||||
write_mhpmcounterh },
|
||||
[CSR_MHPMCOUNTER23H] = { "mhpmcounter23h", mctr32, read_hpmcounterh,
|
||||
write_mhpmcounterh },
|
||||
write_mhpmcounterh },
|
||||
[CSR_MHPMCOUNTER24H] = { "mhpmcounter24h", mctr32, read_hpmcounterh,
|
||||
write_mhpmcounterh },
|
||||
write_mhpmcounterh },
|
||||
[CSR_MHPMCOUNTER25H] = { "mhpmcounter25h", mctr32, read_hpmcounterh,
|
||||
write_mhpmcounterh },
|
||||
write_mhpmcounterh },
|
||||
[CSR_MHPMCOUNTER26H] = { "mhpmcounter26h", mctr32, read_hpmcounterh,
|
||||
write_mhpmcounterh },
|
||||
write_mhpmcounterh },
|
||||
[CSR_MHPMCOUNTER27H] = { "mhpmcounter27h", mctr32, read_hpmcounterh,
|
||||
write_mhpmcounterh },
|
||||
write_mhpmcounterh },
|
||||
[CSR_MHPMCOUNTER28H] = { "mhpmcounter28h", mctr32, read_hpmcounterh,
|
||||
write_mhpmcounterh },
|
||||
write_mhpmcounterh },
|
||||
[CSR_MHPMCOUNTER29H] = { "mhpmcounter29h", mctr32, read_hpmcounterh,
|
||||
write_mhpmcounterh },
|
||||
write_mhpmcounterh },
|
||||
[CSR_MHPMCOUNTER30H] = { "mhpmcounter30h", mctr32, read_hpmcounterh,
|
||||
write_mhpmcounterh },
|
||||
write_mhpmcounterh },
|
||||
[CSR_MHPMCOUNTER31H] = { "mhpmcounter31h", mctr32, read_hpmcounterh,
|
||||
write_mhpmcounterh },
|
||||
write_mhpmcounterh },
|
||||
#endif /* !CONFIG_USER_ONLY */
|
||||
};
|
||||
|
|
|
|||
Loading…
Reference in New Issue