ETRAX: Add a model for the axis devboard88 machine.
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@gmail.com> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6197 c046a42c-6fe2-441c-8c8c-71466251a162
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edgar_igl
parent
de55306582
commit
10c144e2fb
@ -676,7 +676,10 @@ OBJS+= pflash_cfi01.o
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CPPFLAGS += -DHAS_AUDIO -DHAS_AUDIO_CHOICE
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endif
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ifeq ($(TARGET_BASE_ARCH), cris)
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OBJS+= etraxfs.o
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# Boards
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OBJS+= etraxfs.o axis_dev88.o
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# IO blocks
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OBJS+= etraxfs_dma.o
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OBJS+= etraxfs_pic.o
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OBJS+= etraxfs_eth.o
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@ -684,7 +687,7 @@ OBJS+= etraxfs_timer.o
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OBJS+= etraxfs_ser.o
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OBJS+= ptimer.o
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OBJS+= pflash_cfi02.o
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OBJS+= pflash_cfi02.o nand.o
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endif
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ifeq ($(TARGET_BASE_ARCH), sparc)
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ifeq ($(TARGET_ARCH), sparc64)
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276
hw/axis_dev88.c
Normal file
276
hw/axis_dev88.c
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@ -0,0 +1,276 @@
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/*
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* QEMU model for the AXIS devboard 88.
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*
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* Copyright (c) 2009 Edgar E. Iglesias, Axis Communications AB.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#include <time.h>
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#include <sys/time.h>
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#include "hw.h"
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#include "net.h"
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#include "flash.h"
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#include "sysemu.h"
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#include "devices.h"
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#include "boards.h"
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#include "etraxfs.h"
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#define D(x)
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#define DNAND(x)
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struct nand_state_t
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{
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struct nand_flash_s *nand;
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unsigned int rdy:1;
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unsigned int ale:1;
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unsigned int cle:1;
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unsigned int ce:1;
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};
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static struct nand_state_t nand_state;
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static uint32_t nand_readl (void *opaque, target_phys_addr_t addr)
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{
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struct nand_state_t *s = opaque;
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uint32_t r;
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int rdy;
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r = nand_getio(s->nand);
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nand_getpins(s->nand, &rdy);
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s->rdy = rdy;
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DNAND(printf("%s addr=%x r=%x\n", __func__, addr, r));
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return r;
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}
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static void
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nand_writel (void *opaque, target_phys_addr_t addr, uint32_t value)
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{
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struct nand_state_t *s = opaque;
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int rdy;
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DNAND(printf("%s addr=%x v=%x\n", __func__, addr, value));
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nand_setpins(s->nand, s->cle, s->ale, s->ce, 1, 0);
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nand_setio(s->nand, value);
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nand_getpins(s->nand, &rdy);
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s->rdy = rdy;
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}
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static CPUReadMemoryFunc *nand_read[] = {
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&nand_readl,
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&nand_readl,
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&nand_readl,
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};
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static CPUWriteMemoryFunc *nand_write[] = {
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&nand_writel,
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&nand_writel,
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&nand_writel,
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};
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#define RW_PA_DOUT 0
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#define R_PA_DIN 1
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#define RW_PA_OE 2
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struct gpio_state_t
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{
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struct nand_state_t *nand;
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uint32_t regs[0x5c / 4];
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} gpio_state;
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static uint32_t gpio_readl (void *opaque, target_phys_addr_t addr)
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{
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struct gpio_state_t *s = opaque;
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uint32_t r = 0;
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addr >>= 2;
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switch (addr)
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{
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case R_PA_DIN:
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r = s->regs[RW_PA_DOUT] & s->regs[RW_PA_OE];
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/* Encode pins from the nand. */
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r |= s->nand->rdy << 7;
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break;
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default:
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r = s->regs[addr];
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break;
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}
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return r;
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D(printf("%s %x=%x\n", __func__, addr, r));
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}
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static void gpio_writel (void *opaque, target_phys_addr_t addr, uint32_t value)
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{
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struct gpio_state_t *s = opaque;
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D(printf("%s %x=%x\n", __func__, addr, value));
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addr >>= 2;
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switch (addr)
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{
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case RW_PA_DOUT:
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/* Decode nand pins. */
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s->nand->ale = !!(value & (1 << 6));
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s->nand->cle = !!(value & (1 << 5));
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s->nand->ce = !!(value & (1 << 4));
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s->regs[addr] = value;
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break;
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default:
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s->regs[addr] = value;
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break;
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}
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}
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static CPUReadMemoryFunc *gpio_read[] = {
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NULL, NULL,
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&gpio_readl,
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};
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static CPUWriteMemoryFunc *gpio_write[] = {
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NULL, NULL,
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&gpio_writel,
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};
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#define INTMEM_SIZE (128 * 1024)
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static uint32_t bootstrap_pc;
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static void main_cpu_reset(void *opaque)
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{
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CPUState *env = opaque;
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cpu_reset(env);
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env->pc = bootstrap_pc;
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}
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static
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void axisdev88_init (ram_addr_t ram_size, int vga_ram_size,
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const char *boot_device, DisplayState *ds,
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const char *kernel_filename, const char *kernel_cmdline,
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const char *initrd_filename, const char *cpu_model)
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{
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CPUState *env;
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struct etraxfs_pic *pic;
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void *etraxfs_dmac;
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struct etraxfs_dma_client *eth[2] = {NULL, NULL};
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int kernel_size;
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int i;
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int nand_regs;
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int gpio_regs;
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ram_addr_t phys_ram;
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ram_addr_t phys_intmem;
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/* init CPUs */
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if (cpu_model == NULL) {
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cpu_model = "crisv32";
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}
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env = cpu_init(cpu_model);
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qemu_register_reset(main_cpu_reset, env);
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/* allocate RAM */
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phys_ram = qemu_ram_alloc(ram_size);
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cpu_register_physical_memory(0x40000000, ram_size, phys_ram | IO_MEM_RAM);
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/* The ETRAX-FS has 128Kb on chip ram, the docs refer to it as the
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internal memory. */
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phys_intmem = qemu_ram_alloc(INTMEM_SIZE);
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cpu_register_physical_memory(0x38000000, INTMEM_SIZE,
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phys_intmem | IO_MEM_RAM);
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/* Attach a NAND flash to CS1. */
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nand_state.nand = nand_init(NAND_MFR_STMICRO, 0xf1);
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nand_regs = cpu_register_io_memory(0, nand_read, nand_write, &nand_state);
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cpu_register_physical_memory(0x10000000, 0x05000000, nand_regs);
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gpio_state.nand = &nand_state;
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gpio_regs = cpu_register_io_memory(0, gpio_read, gpio_write, &gpio_state);
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cpu_register_physical_memory(0x3001a000, 0x1c, gpio_regs);
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pic = etraxfs_pic_init(env, 0x3001c000);
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etraxfs_dmac = etraxfs_dmac_init(env, 0x30000000, 10);
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for (i = 0; i < 10; i++) {
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/* On ETRAX, odd numbered channels are inputs. */
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etraxfs_dmac_connect(etraxfs_dmac, i, pic->irq + 7 + i, i & 1);
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}
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/* Add the two ethernet blocks. */
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eth[0] = etraxfs_eth_init(&nd_table[0], env, pic->irq + 25, 0x30034000);
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if (nb_nics > 1)
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eth[1] = etraxfs_eth_init(&nd_table[1], env, pic->irq + 26, 0x30036000);
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/* The DMA Connector block is missing, hardwire things for now. */
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etraxfs_dmac_connect_client(etraxfs_dmac, 0, eth[0]);
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etraxfs_dmac_connect_client(etraxfs_dmac, 1, eth[0] + 1);
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if (eth[1]) {
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etraxfs_dmac_connect_client(etraxfs_dmac, 6, eth[1]);
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etraxfs_dmac_connect_client(etraxfs_dmac, 7, eth[1] + 1);
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}
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/* 2 timers. */
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etraxfs_timer_init(env, pic->irq + 0x1b, pic->nmi + 1, 0x3001e000);
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etraxfs_timer_init(env, pic->irq + 0x1b, pic->nmi + 1, 0x3005e000);
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for (i = 0; i < 4; i++) {
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if (serial_hds[i]) {
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etraxfs_ser_init(env, pic->irq + 0x14 + i,
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serial_hds[i], 0x30026000 + i * 0x2000);
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}
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}
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if (kernel_filename) {
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uint64_t entry, high;
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int kcmdline_len;
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/* Boots a kernel elf binary, os/linux-2.6/vmlinux from the axis
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devboard SDK. */
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kernel_size = load_elf(kernel_filename, -0x80000000LL,
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&entry, NULL, &high);
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bootstrap_pc = entry;
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if (kernel_size < 0) {
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/* Takes a kimage from the axis devboard SDK. */
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kernel_size = load_image(kernel_filename, phys_ram_base + 0x4000);
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bootstrap_pc = 0x40004000;
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env->regs[9] = 0x40004000 + kernel_size;
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}
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env->regs[8] = 0x56902387; /* RAM init magic. */
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if (kernel_cmdline && (kcmdline_len = strlen(kernel_cmdline))) {
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if (kcmdline_len > 256) {
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fprintf(stderr, "Too long CRIS kernel cmdline (max 256)\n");
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exit(1);
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}
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pstrcpy_targphys(high, 256, kernel_cmdline);
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/* Let the kernel know we are modifying the cmdline. */
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env->regs[10] = 0x87109563;
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env->regs[11] = high;
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}
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}
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env->pc = bootstrap_pc;
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printf ("pc =%x\n", env->pc);
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printf ("ram size =%ld\n", ram_size);
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}
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QEMUMachine axisdev88_machine = {
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.name = "axis-dev88",
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.desc = "AXIS devboard 88",
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.init = axisdev88_init,
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.ram_require = 0x8000000,
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};
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@ -27,6 +27,7 @@ void register_machines(void);
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/* Axis ETRAX. */
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extern QEMUMachine bareetraxfs_machine;
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extern QEMUMachine axisdev88_machine;
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/* pc.c */
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extern QEMUMachine pc_machine;
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@ -4,6 +4,7 @@
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void register_machines(void)
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{
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qemu_register_machine(&bareetraxfs_machine);
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qemu_register_machine(&axisdev88_machine);
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}
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void cpu_save(QEMUFile *f, void *opaque)
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