OpenRISC Fixes for 7.0
- A few or1ksim fixes and enhancements - A fix for OpenRISC tcg backend around delay slot handling -----BEGIN PGP SIGNATURE----- iQIzBAABCAAdFiEE2cRzVK74bBA6Je/xw7McLV5mJ+QFAmKAWKsACgkQw7McLV5m J+SoFg/8Dlrc2BqjjXw9gpaQ18+3BRI6dMVPqHA22VJks88gykH7UWLUbrCxtKnS SBcIcpzu17nKDdfwYWndqCr0UBM/zM3JzFrTv4QEhTEg6Np7lSM2KVNEhjBPVGoW A7QOjPFrwItWOfAx6hrcczpj+L50iKuWeMW0XnEfqSeDYisxZcSp2yMoe5h3y7bF tlpo+ha/ir/fd2kMlFrQlPWYiWkWM05RLJJOlXhdRMF7hrW5qlHqEB/SVykUTf7V 6fqOFvY6r3vE5OFm0Scgf/k2AJIxwV8qXkBJ5/egv+ZqUidZBQ9nXtOw++vF2AWp eKoU2/c2XIxiF1Xdpgdi6a/CxlLqrr9jraQROB3GpaL9zGQvd//wUCg0F+QLicLv avq4lvNmnat89aXj1DQ+DWpLy0zaZFGmxsPR+KeBJ2wkuEJ3Vd4+uiuAyXnm9M8D wEE8mgFQYsTL1WlgHF4uNTDIx8OLS+4gYlBE3tffRksxyLLwzKHHgAfLdNZvhfx8 QZBuPy+yyO8zjr3RUVUArBs/ukZHP1QwDE6uxmPKV34tvVEbFVeSFY3a1LmYV3w5 mZNALNqf+h5Dq5Qo7f7cGNMrzhL53GTWPNX0MK5+SBDZF3/fpPZyvCr4Zd69Z5tD +YClfWBv8HPjdUf+IFHqyE8rURw/sgNvgB76GpalwcUYXRr7zTM= =tmP4 -----END PGP SIGNATURE----- Merge tag 'or1k-pull-request-20220515' of https://github.com/stffrdhrn/qemu into staging OpenRISC Fixes for 7.0 - A few or1ksim fixes and enhancements - A fix for OpenRISC tcg backend around delay slot handling # -----BEGIN PGP SIGNATURE----- # # iQIzBAABCAAdFiEE2cRzVK74bBA6Je/xw7McLV5mJ+QFAmKAWKsACgkQw7McLV5m # J+SoFg/8Dlrc2BqjjXw9gpaQ18+3BRI6dMVPqHA22VJks88gykH7UWLUbrCxtKnS # SBcIcpzu17nKDdfwYWndqCr0UBM/zM3JzFrTv4QEhTEg6Np7lSM2KVNEhjBPVGoW # A7QOjPFrwItWOfAx6hrcczpj+L50iKuWeMW0XnEfqSeDYisxZcSp2yMoe5h3y7bF # tlpo+ha/ir/fd2kMlFrQlPWYiWkWM05RLJJOlXhdRMF7hrW5qlHqEB/SVykUTf7V # 6fqOFvY6r3vE5OFm0Scgf/k2AJIxwV8qXkBJ5/egv+ZqUidZBQ9nXtOw++vF2AWp # eKoU2/c2XIxiF1Xdpgdi6a/CxlLqrr9jraQROB3GpaL9zGQvd//wUCg0F+QLicLv # avq4lvNmnat89aXj1DQ+DWpLy0zaZFGmxsPR+KeBJ2wkuEJ3Vd4+uiuAyXnm9M8D # wEE8mgFQYsTL1WlgHF4uNTDIx8OLS+4gYlBE3tffRksxyLLwzKHHgAfLdNZvhfx8 # QZBuPy+yyO8zjr3RUVUArBs/ukZHP1QwDE6uxmPKV34tvVEbFVeSFY3a1LmYV3w5 # mZNALNqf+h5Dq5Qo7f7cGNMrzhL53GTWPNX0MK5+SBDZF3/fpPZyvCr4Zd69Z5tD # +YClfWBv8HPjdUf+IFHqyE8rURw/sgNvgB76GpalwcUYXRr7zTM= # =tmP4 # -----END PGP SIGNATURE----- # gpg: Signature made Sat 14 May 2022 06:34:35 PM PDT # gpg: using RSA key D9C47354AEF86C103A25EFF1C3B31C2D5E6627E4 # gpg: Good signature from "Stafford Horne <shorne@gmail.com>" [unknown] # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: D9C4 7354 AEF8 6C10 3A25 EFF1 C3B3 1C2D 5E66 27E4 * tag 'or1k-pull-request-20220515' of https://github.com/stffrdhrn/qemu: target/openrisc: Do not reset delay slot flag on early tb exit hw/openrisc: use right OMPIC size variable hw/openrisc: support 4 serial ports in or1ksim hw/openrisc: page-align FDT address Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
This commit is contained in:
Richard Henderson
commit
10c2a0c5e7
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@ -71,6 +71,10 @@ enum {
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OR1KSIM_ETHOC_IRQ = 4,
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};
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enum {
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OR1KSIM_UART_COUNT = 4
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};
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static const struct MemmapEntry {
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hwaddr base;
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hwaddr size;
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@ -78,7 +82,7 @@ static const struct MemmapEntry {
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[OR1KSIM_DRAM] = { 0x00000000, 0 },
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[OR1KSIM_UART] = { 0x90000000, 0x100 },
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[OR1KSIM_ETHOC] = { 0x92000000, 0x800 },
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[OR1KSIM_OMPIC] = { 0x98000000, 16 },
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[OR1KSIM_OMPIC] = { 0x98000000, OR1KSIM_CPUS_MAX * 8 },
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};
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static struct openrisc_boot_info {
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@ -239,11 +243,13 @@ static void openrisc_sim_ompic_init(Or1ksimState *state, hwaddr base,
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static void openrisc_sim_serial_init(Or1ksimState *state, hwaddr base,
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hwaddr size, int num_cpus,
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OpenRISCCPU *cpus[], int irq_pin)
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OpenRISCCPU *cpus[], int irq_pin,
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int uart_idx)
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{
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void *fdt = state->fdt;
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char *nodename;
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qemu_irq serial_irq;
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char alias[sizeof("uart0")];
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int i;
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if (num_cpus > 1) {
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@ -258,7 +264,8 @@ static void openrisc_sim_serial_init(Or1ksimState *state, hwaddr base,
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serial_irq = get_cpu_irq(cpus, 0, irq_pin);
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}
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serial_mm_init(get_system_memory(), base, 0, serial_irq, 115200,
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serial_hd(0), DEVICE_NATIVE_ENDIAN);
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serial_hd(OR1KSIM_UART_COUNT - uart_idx - 1),
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DEVICE_NATIVE_ENDIAN);
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/* Add device tree node for serial. */
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nodename = g_strdup_printf("/serial@%" HWADDR_PRIx, base);
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@ -271,7 +278,8 @@ static void openrisc_sim_serial_init(Or1ksimState *state, hwaddr base,
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/* The /chosen node is created during fdt creation. */
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qemu_fdt_setprop_string(fdt, "/chosen", "stdout-path", nodename);
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qemu_fdt_setprop_string(fdt, "/aliases", "uart0", nodename);
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snprintf(alias, sizeof(alias), "uart%d", uart_idx);
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qemu_fdt_setprop_string(fdt, "/aliases", alias, nodename);
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g_free(nodename);
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}
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@ -356,7 +364,7 @@ static uint32_t openrisc_load_fdt(Or1ksimState *state, hwaddr load_start,
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}
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/* We put fdt right after the kernel and/or initrd. */
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fdt_addr = ROUND_UP(load_start, 4);
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fdt_addr = TARGET_PAGE_ALIGN(load_start);
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ret = fdt_pack(fdt);
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/* Should only fail if we've built a corrupted tree */
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@ -410,13 +418,15 @@ static void openrisc_sim_init(MachineState *machine)
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if (smp_cpus > 1) {
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openrisc_sim_ompic_init(state, or1ksim_memmap[OR1KSIM_OMPIC].base,
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or1ksim_memmap[OR1KSIM_UART].size,
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or1ksim_memmap[OR1KSIM_OMPIC].size,
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smp_cpus, cpus, OR1KSIM_OMPIC_IRQ);
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}
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openrisc_sim_serial_init(state, or1ksim_memmap[OR1KSIM_UART].base,
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or1ksim_memmap[OR1KSIM_UART].size, smp_cpus, cpus,
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OR1KSIM_UART_IRQ);
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for (n = 0; n < OR1KSIM_UART_COUNT; ++n)
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openrisc_sim_serial_init(state, or1ksim_memmap[OR1KSIM_UART].base +
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or1ksim_memmap[OR1KSIM_UART].size * n,
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or1ksim_memmap[OR1KSIM_UART].size,
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smp_cpus, cpus, OR1KSIM_UART_IRQ, n);
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load_addr = openrisc_load_kernel(ram_size, kernel_filename);
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if (load_addr > 0) {
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@ -21,6 +21,7 @@
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#include "qapi/error.h"
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#include "qemu/qemu-print.h"
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#include "cpu.h"
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#include "exec/exec-all.h"
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static void openrisc_cpu_set_pc(CPUState *cs, vaddr value)
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{
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@ -30,6 +31,15 @@ static void openrisc_cpu_set_pc(CPUState *cs, vaddr value)
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cpu->env.dflag = 0;
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}
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static void openrisc_cpu_synchronize_from_tb(CPUState *cs,
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const TranslationBlock *tb)
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{
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OpenRISCCPU *cpu = OPENRISC_CPU(cs);
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cpu->env.pc = tb->pc;
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}
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static bool openrisc_cpu_has_work(CPUState *cs)
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{
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return cs->interrupt_request & (CPU_INTERRUPT_HARD |
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@ -186,6 +196,7 @@ static const struct SysemuCPUOps openrisc_sysemu_ops = {
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static const struct TCGCPUOps openrisc_tcg_ops = {
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.initialize = openrisc_translate_init,
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.synchronize_from_tb = openrisc_cpu_synchronize_from_tb,
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#ifndef CONFIG_USER_ONLY
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.tlb_fill = openrisc_cpu_tlb_fill,
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