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target/arm: Use tcg_gen_gvec_dup_i64 for LD[1-4]R 

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20181011205206.3552-4-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Richard Henderson 2018-10-24 07:50:18 +01:00 committed by Peter Maydell
parent 7108e255c2
commit 10e0b33c67
1 changed files with 3 additions and 25 deletions
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28
target/arm/translate-a64.c
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@ -3223,36 +3223,14 @@ static void disas_ldst_single_struct(DisasContext *s, uint32_t insn)
for (xs = 0; xs < selem; xs++) {
if (replicate) {
/* Load and replicate to all elements */
uint64_t mulconst;
TCGv_i64 tcg_tmp = tcg_temp_new_i64();
tcg_gen_qemu_ld_i64(tcg_tmp, tcg_addr,
get_mem_index(s), s->be_data + scale);
switch (scale) {
case 0:
mulconst = 0x0101010101010101ULL;
break;
case 1:
mulconst = 0x0001000100010001ULL;
break;
case 2:
mulconst = 0x0000000100000001ULL;
break;
case 3:
mulconst = 0;
break;
default:
g_assert_not_reached();
}
if (mulconst) {
tcg_gen_muli_i64(tcg_tmp, tcg_tmp, mulconst);
}
write_vec_element(s, tcg_tmp, rt, 0, MO_64);
if (is_q) {
write_vec_element(s, tcg_tmp, rt, 1, MO_64);
}
tcg_gen_gvec_dup_i64(scale, vec_full_reg_offset(s, rt),
(is_q + 1) * 8, vec_full_reg_size(s),
tcg_tmp);
tcg_temp_free_i64(tcg_tmp);
clear_vec_high(s, is_q, rt);
} else {
/* Load/store one element per register */
if (is_load) {