target/riscv/kvm: change timer regs size to u64
KVM_REG_RISCV_TIMER regs are always u64 according to the KVM API, but at this moment we'll return u32 regs if we're running a RISCV32 target. Use the kvm_riscv_reg_id_u64() helper in RISCV_TIMER_REG() to fix it. Reported-by: Andrew Jones <ajones@ventanamicro.com> Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Reviewed-by: Andrew Jones <ajones@ventanamicro.com> Message-ID: <20231208183835.2411523-4-dbarboza@ventanamicro.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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@ -88,7 +88,7 @@ static uint64_t kvm_riscv_reg_id_u64(uint64_t type, uint64_t idx)
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#define RISCV_CSR_REG(env, name) kvm_riscv_reg_id(env, KVM_REG_RISCV_CSR, \
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KVM_REG_RISCV_CSR_REG(name))
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#define RISCV_TIMER_REG(env, name) kvm_riscv_reg_id(env, KVM_REG_RISCV_TIMER, \
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#define RISCV_TIMER_REG(name) kvm_riscv_reg_id_u64(KVM_REG_RISCV_TIMER, \
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KVM_REG_RISCV_TIMER_REG(name))
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#define RISCV_FP_F_REG(idx) kvm_riscv_reg_id_u32(KVM_REG_RISCV_FP_F, idx)
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@ -111,17 +111,17 @@ static uint64_t kvm_riscv_reg_id_u64(uint64_t type, uint64_t idx)
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} \
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} while (0)
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#define KVM_RISCV_GET_TIMER(cs, env, name, reg) \
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#define KVM_RISCV_GET_TIMER(cs, name, reg) \
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do { \
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int ret = kvm_get_one_reg(cs, RISCV_TIMER_REG(env, name), ®); \
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int ret = kvm_get_one_reg(cs, RISCV_TIMER_REG(name), ®); \
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if (ret) { \
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abort(); \
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} \
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} while (0)
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#define KVM_RISCV_SET_TIMER(cs, env, name, reg) \
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#define KVM_RISCV_SET_TIMER(cs, name, reg) \
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do { \
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int ret = kvm_set_one_reg(cs, RISCV_TIMER_REG(env, name), ®); \
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int ret = kvm_set_one_reg(cs, RISCV_TIMER_REG(name), ®); \
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if (ret) { \
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abort(); \
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} \
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@ -649,10 +649,10 @@ static void kvm_riscv_get_regs_timer(CPUState *cs)
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return;
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}
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KVM_RISCV_GET_TIMER(cs, env, time, env->kvm_timer_time);
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KVM_RISCV_GET_TIMER(cs, env, compare, env->kvm_timer_compare);
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KVM_RISCV_GET_TIMER(cs, env, state, env->kvm_timer_state);
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KVM_RISCV_GET_TIMER(cs, env, frequency, env->kvm_timer_frequency);
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KVM_RISCV_GET_TIMER(cs, time, env->kvm_timer_time);
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KVM_RISCV_GET_TIMER(cs, compare, env->kvm_timer_compare);
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KVM_RISCV_GET_TIMER(cs, state, env->kvm_timer_state);
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KVM_RISCV_GET_TIMER(cs, frequency, env->kvm_timer_frequency);
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env->kvm_timer_dirty = true;
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}
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@ -666,8 +666,8 @@ static void kvm_riscv_put_regs_timer(CPUState *cs)
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return;
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}
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KVM_RISCV_SET_TIMER(cs, env, time, env->kvm_timer_time);
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KVM_RISCV_SET_TIMER(cs, env, compare, env->kvm_timer_compare);
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KVM_RISCV_SET_TIMER(cs, time, env->kvm_timer_time);
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KVM_RISCV_SET_TIMER(cs, compare, env->kvm_timer_compare);
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/*
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* To set register of RISCV_TIMER_REG(state) will occur a error from KVM
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@ -676,7 +676,7 @@ static void kvm_riscv_put_regs_timer(CPUState *cs)
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* TODO If KVM changes, adapt here.
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*/
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if (env->kvm_timer_state) {
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KVM_RISCV_SET_TIMER(cs, env, state, env->kvm_timer_state);
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KVM_RISCV_SET_TIMER(cs, state, env->kvm_timer_state);
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}
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/*
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@ -685,7 +685,7 @@ static void kvm_riscv_put_regs_timer(CPUState *cs)
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* during the migration.
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*/
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if (migration_is_running(migrate_get_current()->state)) {
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KVM_RISCV_GET_TIMER(cs, env, frequency, reg);
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KVM_RISCV_GET_TIMER(cs, frequency, reg);
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if (reg != env->kvm_timer_frequency) {
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error_report("Dst Hosts timer frequency != Src Hosts");
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}
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