hw/sparc*: Move cpu_check_irqs() to target/sparc/
Since cpu_check_irqs() doesn't reference to anything outside of CPUSPARCState, it better belongs to the architectural code in target/, rather than the hardware specific code in hw/. Note: while we moved the trace events, we don't rename them. Remark: this allows us to build the leon3 machine stand alone, fixing this link failure (because cpu_check_irqs is defined in hw/sparc/sun4m.c which is only built when CONFIG_SUN4M is selected): /usr/bin/ld: target_sparc_win_helper.c.o: in function `cpu_put_psr': target/sparc/win_helper.c:91: undefined reference to `cpu_check_irqs' Suggested-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20210428141655.387430-5-f4bug@amsat.org> Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
This commit is contained in:
Philippe Mathieu-Daudé
Mark Cave-Ayland
parent
5aa7f68a2d
commit
10fb1340b1
@ -170,38 +170,6 @@ static void nvram_init(Nvram *nvram, uint8_t *macaddr,
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}
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}
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void cpu_check_irqs(CPUSPARCState *env)
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{
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CPUState *cs;
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/* We should be holding the BQL before we mess with IRQs */
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g_assert(qemu_mutex_iothread_locked());
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if (env->pil_in && (env->interrupt_index == 0 ||
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(env->interrupt_index & ~15) == TT_EXTINT)) {
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unsigned int i;
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for (i = 15; i > 0; i--) {
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if (env->pil_in & (1 << i)) {
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int old_interrupt = env->interrupt_index;
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env->interrupt_index = TT_EXTINT | i;
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if (old_interrupt != env->interrupt_index) {
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cs = env_cpu(env);
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trace_sun4m_cpu_interrupt(i);
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cpu_interrupt(cs, CPU_INTERRUPT_HARD);
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}
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break;
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}
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}
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} else if (!env->pil_in && (env->interrupt_index & ~15) == TT_EXTINT) {
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cs = env_cpu(env);
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trace_sun4m_cpu_reset_interrupt(env->interrupt_index & 15);
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env->interrupt_index = 0;
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cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD);
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}
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}
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static void cpu_kick_irq(SPARCCPU *cpu)
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{
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CPUSPARCState *env = &cpu->env;
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@ -1,8 +1,6 @@
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# See docs/devel/tracing.txt for syntax documentation.
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# sun4m.c
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sun4m_cpu_interrupt(unsigned int level) "Set CPU IRQ %d"
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sun4m_cpu_reset_interrupt(unsigned int level) "Reset CPU IRQ %d"
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sun4m_cpu_set_irq_raise(int level) "Raise CPU IRQ %d"
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sun4m_cpu_set_irq_lower(int level) "Lower CPU IRQ %d"
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@ -34,72 +34,6 @@
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#define TICK_MAX 0x7fffffffffffffffULL
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void cpu_check_irqs(CPUSPARCState *env)
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{
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CPUState *cs;
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uint32_t pil = env->pil_in |
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(env->softint & ~(SOFTINT_TIMER | SOFTINT_STIMER));
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/* We should be holding the BQL before we mess with IRQs */
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g_assert(qemu_mutex_iothread_locked());
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/* TT_IVEC has a higher priority (16) than TT_EXTINT (31..17) */
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if (env->ivec_status & 0x20) {
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return;
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}
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cs = env_cpu(env);
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/*
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* check if TM or SM in SOFTINT are set
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* setting these also causes interrupt 14
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*/
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if (env->softint & (SOFTINT_TIMER | SOFTINT_STIMER)) {
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pil |= 1 << 14;
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}
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/*
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* The bit corresponding to psrpil is (1<< psrpil),
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* the next bit is (2 << psrpil).
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*/
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if (pil < (2 << env->psrpil)) {
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if (cs->interrupt_request & CPU_INTERRUPT_HARD) {
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trace_sparc64_cpu_check_irqs_reset_irq(env->interrupt_index);
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env->interrupt_index = 0;
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cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD);
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}
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return;
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}
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if (cpu_interrupts_enabled(env)) {
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unsigned int i;
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for (i = 15; i > env->psrpil; i--) {
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if (pil & (1 << i)) {
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int old_interrupt = env->interrupt_index;
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int new_interrupt = TT_EXTINT | i;
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if (unlikely(env->tl > 0 && cpu_tsptr(env)->tt > new_interrupt
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&& ((cpu_tsptr(env)->tt & 0x1f0) == TT_EXTINT))) {
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trace_sparc64_cpu_check_irqs_noset_irq(env->tl,
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cpu_tsptr(env)->tt,
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new_interrupt);
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} else if (old_interrupt != new_interrupt) {
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env->interrupt_index = new_interrupt;
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trace_sparc64_cpu_check_irqs_set_irq(i, old_interrupt,
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new_interrupt);
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cpu_interrupt(cs, CPU_INTERRUPT_HARD);
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}
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break;
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}
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}
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} else if (cs->interrupt_request & CPU_INTERRUPT_HARD) {
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trace_sparc64_cpu_check_irqs_disabled(pil, env->pil_in, env->softint,
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env->interrupt_index);
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env->interrupt_index = 0;
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cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD);
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}
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}
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static void cpu_kick_irq(SPARCCPU *cpu)
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{
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CPUState *cs = CPU(cpu);
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@ -9,10 +9,6 @@ sun4u_iommu_mem_write(uint64_t addr, uint64_t val, int size) "addr: 0x%"PRIx64"
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sun4u_iommu_translate(uint64_t addr, uint64_t trans_addr, uint64_t tte) "xlate 0x%"PRIx64" => pa 0x%"PRIx64" tte: 0x%"PRIx64
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# sparc64.c
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sparc64_cpu_check_irqs_reset_irq(int intno) "Reset CPU IRQ (current interrupt 0x%x)"
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sparc64_cpu_check_irqs_noset_irq(uint32_t tl, uint32_t tt, int intno) "Not setting CPU IRQ: TL=%d current 0x%x >= pending 0x%x"
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sparc64_cpu_check_irqs_set_irq(unsigned int i, int old, int new) "Set CPU IRQ %d old=0x%x new=0x%x"
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sparc64_cpu_check_irqs_disabled(uint32_t pil, uint32_t pil_in, uint32_t softint, int intno) "Interrupts disabled, pil=0x%08x pil_in=0x%08x softint=0x%08x current interrupt 0x%x"
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sparc64_cpu_ivec_raise_irq(int irq) "Raise IVEC IRQ %d"
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sparc64_cpu_ivec_lower_irq(int irq) "Lower IVEC IRQ %d"
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sparc64_cpu_tick_irq_disabled(void) "tick_irq: softint disabled"
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@ -18,6 +18,7 @@
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*/
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#include "qemu/osdep.h"
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#include "qemu/main-loop.h"
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#include "cpu.h"
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#include "trace.h"
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#include "exec/log.h"
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@ -64,6 +65,38 @@ static const char *excp_name_str(int32_t exception_index)
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return excp_names[exception_index];
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}
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void cpu_check_irqs(CPUSPARCState *env)
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{
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CPUState *cs;
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/* We should be holding the BQL before we mess with IRQs */
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g_assert(qemu_mutex_iothread_locked());
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if (env->pil_in && (env->interrupt_index == 0 ||
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(env->interrupt_index & ~15) == TT_EXTINT)) {
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unsigned int i;
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for (i = 15; i > 0; i--) {
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if (env->pil_in & (1 << i)) {
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int old_interrupt = env->interrupt_index;
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env->interrupt_index = TT_EXTINT | i;
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if (old_interrupt != env->interrupt_index) {
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cs = env_cpu(env);
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trace_sun4m_cpu_interrupt(i);
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cpu_interrupt(cs, CPU_INTERRUPT_HARD);
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}
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break;
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}
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}
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} else if (!env->pil_in && (env->interrupt_index & ~15) == TT_EXTINT) {
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cs = env_cpu(env);
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trace_sun4m_cpu_reset_interrupt(env->interrupt_index & 15);
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env->interrupt_index = 0;
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cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD);
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}
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}
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void sparc_cpu_do_interrupt(CPUState *cs)
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{
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SPARCCPU *cpu = SPARC_CPU(cs);
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@ -62,6 +62,72 @@ static const char * const excp_names[0x80] = {
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};
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#endif
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void cpu_check_irqs(CPUSPARCState *env)
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{
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CPUState *cs;
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uint32_t pil = env->pil_in |
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(env->softint & ~(SOFTINT_TIMER | SOFTINT_STIMER));
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/* We should be holding the BQL before we mess with IRQs */
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g_assert(qemu_mutex_iothread_locked());
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/* TT_IVEC has a higher priority (16) than TT_EXTINT (31..17) */
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if (env->ivec_status & 0x20) {
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return;
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}
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cs = env_cpu(env);
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/*
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* check if TM or SM in SOFTINT are set
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* setting these also causes interrupt 14
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*/
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if (env->softint & (SOFTINT_TIMER | SOFTINT_STIMER)) {
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pil |= 1 << 14;
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}
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/*
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* The bit corresponding to psrpil is (1<< psrpil),
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* the next bit is (2 << psrpil).
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*/
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if (pil < (2 << env->psrpil)) {
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if (cs->interrupt_request & CPU_INTERRUPT_HARD) {
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trace_sparc64_cpu_check_irqs_reset_irq(env->interrupt_index);
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env->interrupt_index = 0;
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cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD);
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}
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return;
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}
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if (cpu_interrupts_enabled(env)) {
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unsigned int i;
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for (i = 15; i > env->psrpil; i--) {
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if (pil & (1 << i)) {
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int old_interrupt = env->interrupt_index;
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int new_interrupt = TT_EXTINT | i;
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if (unlikely(env->tl > 0 && cpu_tsptr(env)->tt > new_interrupt
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&& ((cpu_tsptr(env)->tt & 0x1f0) == TT_EXTINT))) {
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trace_sparc64_cpu_check_irqs_noset_irq(env->tl,
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cpu_tsptr(env)->tt,
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new_interrupt);
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} else if (old_interrupt != new_interrupt) {
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env->interrupt_index = new_interrupt;
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trace_sparc64_cpu_check_irqs_set_irq(i, old_interrupt,
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new_interrupt);
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cpu_interrupt(cs, CPU_INTERRUPT_HARD);
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}
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break;
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}
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}
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} else if (cs->interrupt_request & CPU_INTERRUPT_HARD) {
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trace_sparc64_cpu_check_irqs_disabled(pil, env->pil_in, env->softint,
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env->interrupt_index);
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env->interrupt_index = 0;
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cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD);
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}
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}
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void sparc_cpu_do_interrupt(CPUState *cs)
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{
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SPARCCPU *cpu = SPARC_CPU(cs);
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@ -10,10 +10,18 @@ mmu_helper_get_phys_addr_code(uint32_t tl, int mmu_idx, uint64_t prim_context, u
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mmu_helper_get_phys_addr_data(uint32_t tl, int mmu_idx, uint64_t prim_context, uint64_t sec_context, uint64_t address) "tl=%d mmu_idx=%d primary context=0x%"PRIx64" secondary context=0x%"PRIx64" address=0x%"PRIx64
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mmu_helper_mmu_fault(uint64_t address, uint64_t paddr, int mmu_idx, uint32_t tl, uint64_t prim_context, uint64_t sec_context) "Translate at 0x%"PRIx64" -> 0x%"PRIx64", mmu_idx=%d tl=%d primary context=0x%"PRIx64" secondary context=0x%"PRIx64
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# int32_helper.c
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sun4m_cpu_interrupt(unsigned int level) "Set CPU IRQ %d"
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sun4m_cpu_reset_interrupt(unsigned int level) "Reset CPU IRQ %d"
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# int64_helper.c
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int_helper_set_softint(uint32_t softint) "new 0x%08x"
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int_helper_clear_softint(uint32_t softint) "new 0x%08x"
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int_helper_write_softint(uint32_t softint) "new 0x%08x"
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sparc64_cpu_check_irqs_reset_irq(int intno) "Reset CPU IRQ (current interrupt 0x%x)"
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sparc64_cpu_check_irqs_noset_irq(uint32_t tl, uint32_t tt, int intno) "Not setting CPU IRQ: TL=%d current 0x%x >= pending 0x%x"
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sparc64_cpu_check_irqs_set_irq(unsigned int i, int old, int new) "Set CPU IRQ %d old=0x%x new=0x%x"
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sparc64_cpu_check_irqs_disabled(uint32_t pil, uint32_t pil_in, uint32_t softint, int intno) "Interrupts disabled, pil=0x%08x pil_in=0x%08x softint=0x%08x current interrupt 0x%x"
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# win_helper.c
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win_helper_gregset_error(uint32_t pstate) "ERROR in get_gregset: active pstate bits=0x%x"
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