target/arm: Move arm_{ldl,ldq}_ptw to ptw.c
Move the ptw load functions, plus 3 common subroutines: S1_ptw_translate, ptw_attrs_are_device, and regime_translation_big_endian. This also allows get_phys_addr_lpae to become static again. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220604040607.269301-17-richard.henderson@linaro.org Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Richard Henderson
Peter Maydell
parent
3283222acd
commit
11552bb0d9
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@ -10475,12 +10475,6 @@ bool regime_translation_disabled(CPUARMState *env, ARMMMUIdx mmu_idx)
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return (regime_sctlr(env, mmu_idx) & SCTLR_M) == 0;
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}
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static inline bool regime_translation_big_endian(CPUARMState *env,
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ARMMMUIdx mmu_idx)
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{
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return (regime_sctlr(env, mmu_idx) & SCTLR_EE) != 0;
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}
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/* Return the TTBR associated with this translation regime */
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uint64_t regime_ttbr(CPUARMState *env, ARMMMUIdx mmu_idx, int ttbrn)
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{
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@ -10773,141 +10767,6 @@ int get_S1prot(CPUARMState *env, ARMMMUIdx mmu_idx, bool is_aa64,
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return prot_rw | PAGE_EXEC;
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}
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static bool ptw_attrs_are_device(CPUARMState *env, ARMCacheAttrs cacheattrs)
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{
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/*
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* For an S1 page table walk, the stage 1 attributes are always
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* some form of "this is Normal memory". The combined S1+S2
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* attributes are therefore only Device if stage 2 specifies Device.
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* With HCR_EL2.FWB == 0 this is when descriptor bits [5:4] are 0b00,
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* ie when cacheattrs.attrs bits [3:2] are 0b00.
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* With HCR_EL2.FWB == 1 this is when descriptor bit [4] is 0, ie
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* when cacheattrs.attrs bit [2] is 0.
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*/
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assert(cacheattrs.is_s2_format);
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if (arm_hcr_el2_eff(env) & HCR_FWB) {
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return (cacheattrs.attrs & 0x4) == 0;
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} else {
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return (cacheattrs.attrs & 0xc) == 0;
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}
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}
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/* Translate a S1 pagetable walk through S2 if needed. */
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static hwaddr S1_ptw_translate(CPUARMState *env, ARMMMUIdx mmu_idx,
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hwaddr addr, bool *is_secure,
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ARMMMUFaultInfo *fi)
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{
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if (arm_mmu_idx_is_stage1_of_2(mmu_idx) &&
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!regime_translation_disabled(env, ARMMMUIdx_Stage2)) {
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target_ulong s2size;
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hwaddr s2pa;
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int s2prot;
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int ret;
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ARMMMUIdx s2_mmu_idx = *is_secure ? ARMMMUIdx_Stage2_S
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: ARMMMUIdx_Stage2;
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ARMCacheAttrs cacheattrs = {};
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MemTxAttrs txattrs = {};
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ret = get_phys_addr_lpae(env, addr, MMU_DATA_LOAD, s2_mmu_idx, false,
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&s2pa, &txattrs, &s2prot, &s2size, fi,
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&cacheattrs);
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if (ret) {
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assert(fi->type != ARMFault_None);
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fi->s2addr = addr;
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fi->stage2 = true;
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fi->s1ptw = true;
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fi->s1ns = !*is_secure;
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return ~0;
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}
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if ((arm_hcr_el2_eff(env) & HCR_PTW) &&
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ptw_attrs_are_device(env, cacheattrs)) {
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/*
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* PTW set and S1 walk touched S2 Device memory:
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* generate Permission fault.
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*/
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fi->type = ARMFault_Permission;
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fi->s2addr = addr;
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fi->stage2 = true;
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fi->s1ptw = true;
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fi->s1ns = !*is_secure;
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return ~0;
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}
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if (arm_is_secure_below_el3(env)) {
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/* Check if page table walk is to secure or non-secure PA space. */
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if (*is_secure) {
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*is_secure = !(env->cp15.vstcr_el2.raw_tcr & VSTCR_SW);
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} else {
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*is_secure = !(env->cp15.vtcr_el2.raw_tcr & VTCR_NSW);
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}
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} else {
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assert(!*is_secure);
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}
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addr = s2pa;
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}
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return addr;
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}
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/* All loads done in the course of a page table walk go through here. */
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uint32_t arm_ldl_ptw(CPUState *cs, hwaddr addr, bool is_secure,
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ARMMMUIdx mmu_idx, ARMMMUFaultInfo *fi)
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{
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ARMCPU *cpu = ARM_CPU(cs);
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CPUARMState *env = &cpu->env;
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MemTxAttrs attrs = {};
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MemTxResult result = MEMTX_OK;
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AddressSpace *as;
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uint32_t data;
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addr = S1_ptw_translate(env, mmu_idx, addr, &is_secure, fi);
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attrs.secure = is_secure;
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as = arm_addressspace(cs, attrs);
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if (fi->s1ptw) {
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return 0;
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}
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if (regime_translation_big_endian(env, mmu_idx)) {
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data = address_space_ldl_be(as, addr, attrs, &result);
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} else {
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data = address_space_ldl_le(as, addr, attrs, &result);
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}
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if (result == MEMTX_OK) {
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return data;
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}
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fi->type = ARMFault_SyncExternalOnWalk;
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fi->ea = arm_extabort_type(result);
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return 0;
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}
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uint64_t arm_ldq_ptw(CPUState *cs, hwaddr addr, bool is_secure,
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ARMMMUIdx mmu_idx, ARMMMUFaultInfo *fi)
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{
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ARMCPU *cpu = ARM_CPU(cs);
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CPUARMState *env = &cpu->env;
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MemTxAttrs attrs = {};
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MemTxResult result = MEMTX_OK;
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AddressSpace *as;
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uint64_t data;
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addr = S1_ptw_translate(env, mmu_idx, addr, &is_secure, fi);
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attrs.secure = is_secure;
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as = arm_addressspace(cs, attrs);
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if (fi->s1ptw) {
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return 0;
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}
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if (regime_translation_big_endian(env, mmu_idx)) {
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data = address_space_ldq_be(as, addr, attrs, &result);
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} else {
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data = address_space_ldq_le(as, addr, attrs, &result);
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}
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if (result == MEMTX_OK) {
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return data;
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}
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fi->type = ARMFault_SyncExternalOnWalk;
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fi->ea = arm_extabort_type(result);
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return 0;
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}
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/*
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* check_s2_mmu_setup
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* @cpu: ARMCPU
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160
target/arm/ptw.c
160
target/arm/ptw.c
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@ -15,6 +15,154 @@
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#include "ptw.h"
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static bool get_phys_addr_lpae(CPUARMState *env, uint64_t address,
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MMUAccessType access_type, ARMMMUIdx mmu_idx,
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bool s1_is_el0, hwaddr *phys_ptr,
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MemTxAttrs *txattrs, int *prot,
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target_ulong *page_size_ptr,
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ARMMMUFaultInfo *fi, ARMCacheAttrs *cacheattrs)
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__attribute__((nonnull));
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static bool regime_translation_big_endian(CPUARMState *env, ARMMMUIdx mmu_idx)
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{
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return (regime_sctlr(env, mmu_idx) & SCTLR_EE) != 0;
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}
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static bool ptw_attrs_are_device(CPUARMState *env, ARMCacheAttrs cacheattrs)
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{
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/*
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* For an S1 page table walk, the stage 1 attributes are always
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* some form of "this is Normal memory". The combined S1+S2
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* attributes are therefore only Device if stage 2 specifies Device.
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* With HCR_EL2.FWB == 0 this is when descriptor bits [5:4] are 0b00,
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* ie when cacheattrs.attrs bits [3:2] are 0b00.
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* With HCR_EL2.FWB == 1 this is when descriptor bit [4] is 0, ie
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* when cacheattrs.attrs bit [2] is 0.
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*/
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assert(cacheattrs.is_s2_format);
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if (arm_hcr_el2_eff(env) & HCR_FWB) {
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return (cacheattrs.attrs & 0x4) == 0;
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} else {
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return (cacheattrs.attrs & 0xc) == 0;
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}
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}
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/* Translate a S1 pagetable walk through S2 if needed. */
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static hwaddr S1_ptw_translate(CPUARMState *env, ARMMMUIdx mmu_idx,
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hwaddr addr, bool *is_secure,
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ARMMMUFaultInfo *fi)
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{
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if (arm_mmu_idx_is_stage1_of_2(mmu_idx) &&
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!regime_translation_disabled(env, ARMMMUIdx_Stage2)) {
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target_ulong s2size;
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hwaddr s2pa;
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int s2prot;
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int ret;
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ARMMMUIdx s2_mmu_idx = *is_secure ? ARMMMUIdx_Stage2_S
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: ARMMMUIdx_Stage2;
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ARMCacheAttrs cacheattrs = {};
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MemTxAttrs txattrs = {};
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ret = get_phys_addr_lpae(env, addr, MMU_DATA_LOAD, s2_mmu_idx, false,
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&s2pa, &txattrs, &s2prot, &s2size, fi,
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&cacheattrs);
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if (ret) {
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assert(fi->type != ARMFault_None);
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fi->s2addr = addr;
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fi->stage2 = true;
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fi->s1ptw = true;
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fi->s1ns = !*is_secure;
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return ~0;
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}
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if ((arm_hcr_el2_eff(env) & HCR_PTW) &&
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ptw_attrs_are_device(env, cacheattrs)) {
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/*
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* PTW set and S1 walk touched S2 Device memory:
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* generate Permission fault.
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*/
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fi->type = ARMFault_Permission;
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fi->s2addr = addr;
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fi->stage2 = true;
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fi->s1ptw = true;
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fi->s1ns = !*is_secure;
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return ~0;
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}
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if (arm_is_secure_below_el3(env)) {
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/* Check if page table walk is to secure or non-secure PA space. */
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if (*is_secure) {
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*is_secure = !(env->cp15.vstcr_el2.raw_tcr & VSTCR_SW);
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} else {
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*is_secure = !(env->cp15.vtcr_el2.raw_tcr & VTCR_NSW);
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}
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} else {
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assert(!*is_secure);
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}
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addr = s2pa;
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}
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return addr;
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}
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/* All loads done in the course of a page table walk go through here. */
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static uint32_t arm_ldl_ptw(CPUState *cs, hwaddr addr, bool is_secure,
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ARMMMUIdx mmu_idx, ARMMMUFaultInfo *fi)
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{
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ARMCPU *cpu = ARM_CPU(cs);
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CPUARMState *env = &cpu->env;
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MemTxAttrs attrs = {};
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MemTxResult result = MEMTX_OK;
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AddressSpace *as;
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uint32_t data;
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addr = S1_ptw_translate(env, mmu_idx, addr, &is_secure, fi);
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attrs.secure = is_secure;
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as = arm_addressspace(cs, attrs);
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if (fi->s1ptw) {
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return 0;
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}
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if (regime_translation_big_endian(env, mmu_idx)) {
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data = address_space_ldl_be(as, addr, attrs, &result);
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} else {
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data = address_space_ldl_le(as, addr, attrs, &result);
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}
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if (result == MEMTX_OK) {
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return data;
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}
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fi->type = ARMFault_SyncExternalOnWalk;
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fi->ea = arm_extabort_type(result);
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return 0;
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}
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static uint64_t arm_ldq_ptw(CPUState *cs, hwaddr addr, bool is_secure,
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ARMMMUIdx mmu_idx, ARMMMUFaultInfo *fi)
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{
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ARMCPU *cpu = ARM_CPU(cs);
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CPUARMState *env = &cpu->env;
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MemTxAttrs attrs = {};
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MemTxResult result = MEMTX_OK;
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AddressSpace *as;
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uint64_t data;
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addr = S1_ptw_translate(env, mmu_idx, addr, &is_secure, fi);
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attrs.secure = is_secure;
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as = arm_addressspace(cs, attrs);
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if (fi->s1ptw) {
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return 0;
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}
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if (regime_translation_big_endian(env, mmu_idx)) {
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data = address_space_ldq_be(as, addr, attrs, &result);
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} else {
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data = address_space_ldq_le(as, addr, attrs, &result);
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}
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if (result == MEMTX_OK) {
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return data;
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}
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fi->type = ARMFault_SyncExternalOnWalk;
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fi->ea = arm_extabort_type(result);
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return 0;
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}
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static bool get_level1_table_address(CPUARMState *env, ARMMMUIdx mmu_idx,
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uint32_t *table, uint32_t address)
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{
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@ -338,12 +486,12 @@ do_fault:
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* @fi: set to fault info if the translation fails
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* @cacheattrs: (if non-NULL) set to the cacheability/shareability attributes
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*/
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bool get_phys_addr_lpae(CPUARMState *env, uint64_t address,
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MMUAccessType access_type, ARMMMUIdx mmu_idx,
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bool s1_is_el0,
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hwaddr *phys_ptr, MemTxAttrs *txattrs, int *prot,
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target_ulong *page_size_ptr,
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ARMMMUFaultInfo *fi, ARMCacheAttrs *cacheattrs)
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static bool get_phys_addr_lpae(CPUARMState *env, uint64_t address,
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MMUAccessType access_type, ARMMMUIdx mmu_idx,
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bool s1_is_el0, hwaddr *phys_ptr,
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MemTxAttrs *txattrs, int *prot,
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target_ulong *page_size_ptr,
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ARMMMUFaultInfo *fi, ARMCacheAttrs *cacheattrs)
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{
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ARMCPU *cpu = env_archcpu(env);
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CPUState *cs = CPU(cpu);
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@ -13,11 +13,6 @@
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extern const uint8_t pamax_map[7];
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uint32_t arm_ldl_ptw(CPUState *cs, hwaddr addr, bool is_secure,
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ARMMMUIdx mmu_idx, ARMMMUFaultInfo *fi);
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uint64_t arm_ldq_ptw(CPUState *cs, hwaddr addr, bool is_secure,
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ARMMMUIdx mmu_idx, ARMMMUFaultInfo *fi);
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bool regime_is_user(CPUARMState *env, ARMMMUIdx mmu_idx);
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bool regime_translation_disabled(CPUARMState *env, ARMMMUIdx mmu_idx);
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uint64_t regime_ttbr(CPUARMState *env, ARMMMUIdx mmu_idx, int ttbrn);
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@ -40,13 +35,5 @@ int get_S2prot(CPUARMState *env, int s2ap, int xn, bool s1_is_el0);
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int get_S1prot(CPUARMState *env, ARMMMUIdx mmu_idx, bool is_aa64,
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int ap, int ns, int xn, int pxn);
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bool get_phys_addr_lpae(CPUARMState *env, uint64_t address,
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MMUAccessType access_type, ARMMMUIdx mmu_idx,
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bool s1_is_el0,
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hwaddr *phys_ptr, MemTxAttrs *txattrs, int *prot,
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target_ulong *page_size_ptr,
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ARMMMUFaultInfo *fi, ARMCacheAttrs *cacheattrs)
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__attribute__((nonnull));
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#endif /* !CONFIG_USER_ONLY */
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#endif /* TARGET_ARM_PTW_H */
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